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88 commits

Author SHA1 Message Date
whitequark 9ea3ff7ae2 build.plat: bypass tool detection if NMIGEN_*_env is set. 
It's not practical to detect tools within the toolchain environment
for various reasons, so just assume the tools are there if the user
says they are.

Before this commit, the tools would be searched outside the toolchain
environment, which of course would always fail for Vivado, ISE, etc.
 2019-09-12 21:56:48 +00:00
whitequark c8f8c09f29 vendor.xilinx_7series: Vivado requires bash on *nix as well. 2019-09-12 21:49:08 +00:00
whitequark 8c30147e39 build.plat,vendor: allow clock constraints on arbitrary signals. 
Currently only done for Synopsys based toolchains (i.e. not nextpnr).

Refs #88.
 2019-09-11 23:35:43 +00:00
Darrell Harmon 27cedf4302 vendor.lattice_ecp5: pass ecppack_opts to ecppack. 2019-09-10 03:32:36 +00:00
Emily c4e8ac734f _toolchain,build.plat,vendor.*: add required_tools list and checks. 2019-08-31 00:05:47 +00:00
whitequark 4e91710933 vendor.lattice_ecp5: drive GSR synchronous to user clock by default. 
Fixes #167.
 2019-08-30 14:26:49 +00:00
whitequark b4b5d9e2ef vendor.lattice_ecp5: revert default toolchain to Trellis. 
This was unintentionally changed in 7fc1058e.
 2019-08-25 08:07:00 +00:00
whitequark 7fc1058ed2 vendor.lattice_ecp5: add Diamond support. 2019-08-22 21:36:24 +00:00
whitequark c77274c1ad vendor: eliminate unnecessary LUT instantiation. 
Fixes #165.
 2019-08-22 21:29:20 +00:00
Darrell Harmon 6737ef79f9 vendor.xilinx_series7: use STARTUPE2, not STARTUPE3. 
STARTUPE3 is for Ultrascale.
 2019-08-21 22:25:55 +00:00
whitequark 5889e62668 vendor.lattice_ice40: remove --placer heap default option. 
It is not the place of nMigen to decide on this default, since both
SA and HeAP have valid uses that are not covered by the other.
 2019-08-21 21:32:38 +00:00
whitequark 531040d2fd vendor: style. NFC. 2019-08-21 21:32:36 +00:00
whitequark 25b280dba1 build.plat: remove TemplatedPlatform.unix_interpreter. 
Vendor toolchains generally require far more workarounds than this,
and we already have a perfectly fine way of overriding templates.
 2019-08-21 21:02:13 +00:00
whitequark 77012fc143 vendor.lattice_ice40: use a local clock domain in create_missing_domain(). 2019-08-19 21:46:44 +00:00
whitequark 1b379a513c vendor.lattice_ice40: add iCE5LP2K support. 2019-08-07 09:25:20 +00:00
whitequark cfbc678508 vendor.lattice_ice40: add iCE40UP3K support. 2019-08-07 09:06:27 +00:00
whitequark 9c35e44e4a vendor.lattice_ice40: add iCE5LP1K support. 2019-08-07 09:01:11 +00:00
whitequark 434b686d5e vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic. 
On Xilinx devices, flip-flops are reset to their initial state with
an internal global reset network, but this network is deasserted
asynchronously to user clocks. Use BUFGCE and STARTUP to hold default
clock low until after GWE is deasserted.
 2019-08-04 23:28:09 +00:00
whitequark 3d7214cb70 vendor.xilinx_spartan_3_6: reconsider bitgen defaults. 
Previously changed in 27063a3b.

I haven't realized the .bin file is the same as the .bit file without
a small header. That means generating it is free and it's just easier
to let programming tools to be able to always rely on its existence.
 2019-08-04 23:28:09 +00:00
whitequark 27063a3bd3 vendor.xilinx_spartan_3_6: set bitgen defaults to -g Binary:Yes -g Compress. 
* `-g Binary:Yes` should be overridable.
  * `-g Compress` is a good default.
 2019-08-04 14:18:49 +00:00
whitequark 65da905c15 vendor.xilinx_spartan_3_6: always use -w for map/par/bitgen. 
-w stands for "override output file", and supplying user options
should not remove it.
 2019-08-04 14:12:02 +00:00
whitequark 15e8dfe532 vendor.xilinx_spartan_3_6: do not use retiming by default. 
This was added in b404d603, probably by mistake, and is certainly
wrong given that we do not (yet) correctly mark CDC FFs.
 2019-08-04 13:48:33 +00:00
whitequark 6b025df12c vendor.xilinx_spartan_3_6: force use of bash on UNIX. 2019-08-04 13:20:54 +00:00
whitequark 34a97b2751 vendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins. 2019-08-04 00:30:50 +00:00
whitequark 999a2f612a vendor.lattice_ice40: add missing signal indexing. 2019-08-03 22:59:33 +00:00
whitequark 8854ca03ae build.plat,vendor: automatically create sync domain from default_clk. 
But only if it is not defined by the programmer.

Closes #57.
 2019-08-03 18:36:58 +00:00
N. Engelhardt 5fd8a796ae vendor: don't emit duplicate iobuf submodule names. 
These are no longer allowed after commit 698b005.
 2019-07-21 07:49:21 +00:00
Alain Péteut 31c54d32ef vendor.xilinx_7series: generate also binary bitfile. 
Fixes #139.
 2019-07-07 21:36:32 +00:00
William D. Jones b404d603fb vendor.xilinx_spartan_3_6: Add Spartan3A family support. 2019-07-07 20:44:48 +00:00
whitequark cb02a452e9 vendor.lattice_ecp5: don't leave LUT inputs disconnected. 
This causes YosysHQ/nextpnr#301.

Fixes #136.
 2019-07-07 02:34:22 +00:00
whitequark 146f3cb684 build.plat: source a script with toolchain environment. 
Fixes #131.
 2019-07-07 00:44:28 +00:00
whitequark 1ee21d2007 build.plat, vendor.*: don't join strings passed as _opts overrides. 
Right now an array is expected in any _opts overrides, and if it is
actually a string (because it is passed via an environment variable,
usually), awkwardness results as each character is joined with ` `.

Fixes #130.
 2019-07-06 23:09:46 +00:00
Staf Verhaegen 2829d04033 vendor.xilinx_{7series,spartan6}: Support extra VHDL files. 2019-07-04 21:13:33 +00:00
whitequark 33f21628bb vendor: give names to IO buffer instances. 
Fixes #123.
 2019-07-03 14:43:03 +00:00
Sebastien Bourdeauducq 9a1048af50 lattice_ecp5: fix get_input 2019-07-03 10:25:32 +08:00
Alain Péteut 20553b1478 build.plat: add iter_extra_files method. 
* vendor.*: employ iter_extra_files.
 2019-07-02 18:25:29 +00:00
Alain Péteut b67f5cfa65 vendor.xilinx_7series: read extra .xdc files. 2019-07-02 08:23:37 +00:00
whitequark 6454378fe7 vendor.lattice_ice40: fix instance of negedge FF due to a typo. 2019-06-28 07:05:20 +00:00
whitequark f60ceb349b vendor.xilinx_{spartan6,7series}: speedgrade→speed. 
For consistency with ECP5.
 2019-06-25 15:51:52 +00:00
whitequark 0a145ed2d9 vendor.lattice_ecp5: implement. 
Note that because of issues with Yosys and nextpnr, it is not yet
possible to use either SDR or DDR I/O.
 2019-06-25 15:48:07 +00:00
whitequark 23ed888857 vendor.lattice_ice40: use different --package for 4k devices. 2019-06-19 06:09:08 +00:00
Jean-François Nguyen b3c5ff7e95 vendor.xilinx_7series: fix IOB packing. 2019-06-17 20:48:46 +00:00
whitequark 3fc5f170e6 vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly. 
Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.
 2019-06-17 15:47:56 +00:00
whitequark 2a8e7bc6f2 vendor.xilinx_{7series,spartan6}: cleanup. NFC. 
Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.
 2019-06-17 15:47:56 +00:00
whitequark 8b34602d91 vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly. 
Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.
 2019-06-17 15:47:56 +00:00
whitequark 70bbfecf6d vendor.lattice_ice40: never place an inverter on global buffer output. 
This would make `pin.i` not a global network anymore, which is likely
undesirable if an explicit Attrs(GLOBAL=1) is specified.
 2019-06-14 20:44:02 +00:00
Jean-François Nguyen 01a3101fd3 vendor.xilinx_7series: implement inverters. 2019-06-13 15:14:09 +00:00
Jean-François Nguyen 412781e0c3 vendor.xilinx_spartan6: implement DDR I/O buffers and inverters. 2019-06-13 15:13:31 +00:00
whitequark 6beba3a48b Simplify code by using Signal.like(name_suffix="..") appropriately. 2019-06-12 22:28:45 +00:00
Jean-François Nguyen 3b303c3334 vendor.xilinx_7series: implement DDR I/O buffers. 2019-06-12 19:55:10 +00:00