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196 commits

Author SHA1 Message Date
whitequark eb04a2509e hdl.mem,lib,examples: use Signal.range(). 2019-09-08 12:19:13 +00:00
whitequark ccfbccc044 hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...). 
Fixes #196.
 2019-09-08 12:10:31 +00:00
whitequark 943ce317af hdl.ast,back.rtlil: implement Cover. 
Fixes #194.
 2019-09-03 01:32:24 +00:00
whitequark 2e20622046 hdl.cd: add negedge clock domains. 
Fixes #185.
 2019-08-31 22:05:48 +00:00
Emily c4e8ac734f _toolchain,build.plat,vendor.*: add required_tools list and checks. 2019-08-31 00:05:47 +00:00
whitequark a4b58cbf3a build.dsl: allow both str and int resource attributes. 2019-08-30 08:35:52 +00:00
Emily 98278a044d test.tools: use _toolchain.get_tool. 2019-08-28 11:52:16 +00:00
whitequark 72cf4ca991 back.pysim: implement sim.add_clock(if_exists=True). 2019-08-23 08:53:48 +00:00
whitequark 906385c7f8 back.pysim: don't crash when trying to drive a nonexistent domain clock. 2019-08-23 08:37:59 +00:00
William D. Jones c934fc66e9 test.test_examples: Convert pathlib-specific class to string. 
subprocess.check_call iterates over its arguments to check for spaces
and tabs, and on Windows, the pathlib-specific WindowsPath is not
iterable.
 2019-08-20 00:54:10 +00:00
whitequark 13316053e3 build.plat, hdl.ir: coordinate missing domain creation. 
Platform.prepare() was completely broken after addition of local
clock domains, and only really worked before by a series of
accidents because there was a circular dependency between creation
of missing domains, fragment preparation, and insertion of pin
subfragments.

This commit untangles the dependency by adding a separate public
method Fragment.create_missing_domains(), used in build.plat.

It also makes DomainCollector consider both used and defined domains,
such that it will work on fragments before domain propagation, since
create_missing_domains() can be called by user code before prepare().

The fragment driving missing clock domain is not flattened anymore,
because flattening does not work well combined with local domains.
 2019-08-19 22:52:01 +00:00
whitequark 003ba3b45f hdl.cd: implement local clock domains. 
Closes #175.
 2019-08-19 21:44:33 +00:00
whitequark 69d36dc139 hdl.xfrm: lower resets in DomainLowerer as well. 
Changed in preparation for introducing local clock domains.

Also makes elaboration about 15% faster.
 2019-08-19 21:44:30 +00:00
whitequark 404f99f022 hdl.xfrm: consider fragment's own domains in DomainLowerer. 
Changed in preparation for introducing local clock domains.
 2019-08-19 21:07:02 +00:00
whitequark 32bfbb11cb formal→asserts 
Closes #171.
 2019-08-19 20:23:24 +00:00
Robin Heinemann 8e048c5a7c build.dsl: add conn argument to Connector. 2019-08-18 19:56:25 +00:00
whitequark ed7e07c6c1 hdl.ast: implement Initial. 
This is the last remaining part for first-class formal support.
 2019-08-15 02:53:07 +00:00
whitequark fa0fa056ba hdl.xfrm: CEInserter→EnableInserter. 
Fixes #166.
 2019-08-12 13:39:26 +00:00
whitequark 99d205494a hdl.dsl: reword m.If(~True) warning to be more clear. 
Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.
 2019-08-03 18:52:24 +00:00
whitequark e0b54b417e hdl.ir: allow adding more than one domain in missing domain callback. 
This is useful for injecting complex power-on reset logic.
 2019-08-03 18:19:40 +00:00
whitequark 9c28b61d9f hdl.ir: don't expose as ports missing domains added via elaboratables. 
The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
 2019-08-03 16:39:21 +00:00
whitequark cea92e9531 hdl.ir: allow returning elaboratables from missing domain callback. 
This allows e.g. injecting a clock/reset generator in platform build
code on demand (i.e. if the domain is not instantiated manually).

See #57.
 2019-08-03 15:44:02 +00:00
whitequark fc846532c7 hdl.ir: raise DomainError if a domain is used but not defined. 
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
 2019-08-03 15:31:24 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. 
See #57.
 2019-08-03 14:54:20 +00:00
whitequark ace2b5ff0a hdl.dsl: warn on suspicious statements like m.If(~True):. 
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.

Fixes #159.
 2019-08-03 14:00:29 +00:00
whitequark ab5426ce74 Improve test added in 29fee01f to not leak warnings. 2019-08-03 13:44:44 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select. 
Fixes #148.
 2019-08-03 13:07:06 +00:00
whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None. 
Fixes #164.
 2019-08-03 12:30:39 +00:00
whitequark 995e4adb8c hdl.xfrm: handle mem.{Read,Write}Port in CEInserter. 
Fixes #154.
 2019-07-31 05:20:05 +00:00
N. Engelhardt 698b005182 hdl.dsl: add getters to m.submodules. 2019-07-19 12:39:47 +00:00
William D. Jones 6ee760e83f build.dsl: Add optional name_suffix to Resource.family. 2019-07-10 15:41:23 +00:00
whitequark 367ad5aee7 build.dsl: add Resource.family abstraction. 2019-07-09 02:44:03 +00:00
whitequark 7b4fbf8e01 build.{dsl,res}: allow platform-dependent attributes using callables. 
Fixes #132.
 2019-07-08 11:15:04 +00:00
whitequark 0ab0a74ec1 hdl.rec: respect modifications to signals in Record.like(). 
Fixes #126.
 2019-07-08 10:59:15 +00:00
whitequark 0b844da4cf build.{dsl,res}: allow removing attributes from subsignals. 
This is useful when most attributes in a large composite resource
are the same, but a few signals are different, and also when building
abstractions around resources.

Fixes #128.
 2019-07-08 10:42:10 +00:00
whitequark f0c1c2cfeb build.dsl: allow assertions on subsignal widths. 
This is useful when building abstractions around resources where
the pin names are user-specified.

Fixes #129.
 2019-07-08 10:42:06 +00:00
whitequark a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. 
Fixes #125.
 2019-07-08 10:26:49 +00:00
whitequark 5c63177fc2 test: generate examples to verilog as part of unit tests. 
This is to make sure 806a62c2 doesn't happen again.
 2019-07-08 10:12:26 +00:00
whitequark da1f58b7ae hdl.dsl: further clarify error message for incorrect nesting. 
Fixes #133.
 2019-07-07 01:03:59 +00:00
whitequark cb8be4a1b0 hdl.dsl: clarify error message for incorrect nesting. 
Refs #133.
 2019-07-07 00:59:57 +00:00
whitequark 3388b5b085 hdl.dsl: gracefully handle FSM with no states. 2019-07-07 00:59:34 +00:00
whitequark b471e33d7f build.res: detect physical conflicts earlier. 
This is useful for two reasons:
  1. nMigen can provide better error messages than the platform and
     do it earlier in the build pipeline.
  2. Many platforms handle diffpairs by only constraining the P pin;
     the N pin is completely ignored. If this is undetected,
     downstream users (human or software) can rely on this
     information assuming it is correct and introduce more errors.
     (Of course, this will not catch every mistake, but the most
     common is a copy-paste issue, and that will handle it.)

Fixes #124.
 2019-07-03 15:07:44 +00:00
whitequark 0ab215e5ed hdl.ast: recognize a Enum used as decoder and format it better. 2019-07-02 19:34:44 +00:00
whitequark 6b843b5be6 hdl.rec: implement slicing by component names. 
Fixes #121.
 2019-07-02 17:46:53 +00:00
whitequark 34f110100a hdl.rec: implement Record.like. 
Fixes #120.
 2019-07-02 17:46:53 +00:00
whitequark 94e8f479a5 hdl.mem: use read_port(domain="comb") for asynchronous read ports. 
This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).

Fixes #116.
 2019-07-01 19:56:49 +00:00
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
 2019-06-28 04:37:08 +00:00
whitequark 48d4ee4031 hdl.ir, back.rtlil: allow specifying attributes on instances. 
Fixes #107.
 2019-06-28 04:14:38 +00:00
whitequark e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. 
This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase
 2019-06-25 22:01:14 +00:00
whitequark e52b15d236 hdl.ast: add name_suffix=".." option to Signal.like(). 
This simplifies creation of related signals with nice names during
metaprogramming, e.g.

  def make_ff(m, sig):
      sig_ff = Signal.like(sig, name_suffix="_ff")
      m.d.sync += sig_ff.eq(sig)
      return sig_ff
 2019-06-12 22:26:57 +00:00