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  • 0a2a7025a6 hdl.xfrm: allow using FragmentTransformer on any elaboratable. whitequark 2019-04-10 00:23:11 +0000
  • 49eef77c53 hdl: remove deprecated get_fragment() and lower() methods. whitequark 2019-04-09 23:53:43 +0000
  • a74cacdc69 hdl.ast: handle a common typo, such as Signal(1, True). whitequark 2019-04-03 14:59:01 +0000
  • c9c9307a5e test_sim: add missing add_process(). whitequark 2019-03-28 17:50:14 +0000
  • 23a07b955f lib.cdc: add optional reset to MultiReg, and document its use cases. Luke Wren 2019-03-19 03:36:55 +0000
  • a57c72d606 back.rtlil: fix off-by-one in Part legalization. whitequark 2019-03-28 05:12:02 +0000
  • 3c95299c4e hdl.rec: separate record and signal name with __, not _. anuejn 2019-03-25 15:26:00 +0100
  • 81ee2db163 hdl.ast: fix typo. whitequark 2019-03-25 10:49:29 +0000
  • d69a4e29a8 examples.por: fix typo Alain Péteut 2019-03-11 18:11:51 +0100
  • 4027317835 lib.fifo: register GrayEncoder output before CDC. whitequark 2019-03-03 18:23:51 +0000
  • e93bf4bf4b tracer: factor out get_var_name(default=). whitequark 2019-02-15 14:15:02 +0000
  • cac4b10b82 hdl.rec: remove __slots__. whitequark 2019-02-15 14:00:42 +0000
  • 342bdbe75a setup.py: constrain Python version Alain Péteut 2019-02-22 09:45:28 +0100
  • 8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. whitequark 2019-02-14 20:52:42 +0000
  • 43e4833ddb back.rtlil: accept ast.Const as cell parameter. whitequark 2019-01-26 23:25:54 +0000
  • bc5a127fd2 hdl.ast: fix ValueKey for Cat. whitequark 2019-01-26 23:25:34 +0000
  • e844b0e095 compat.fhdl.module: fix typo. whitequark 2019-01-26 23:08:55 +0000
  • ce7ba70462 compat.fhdl.specials: fix __all__ list. whitequark 2019-01-26 22:59:33 +0000
  • 6cd9f7db19 compat.genlib.resetsync: add shim for AsyncResetSynchronizer. whitequark 2019-01-26 18:24:12 +0000
  • 2fb85a6170 compat.fifo: fix _FIFOInterface deprecation wrapper. whitequark 2019-01-26 18:23:58 +0000
  • f44ca291c1 lib.cdc: add ResetSynchronizer. whitequark 2019-01-26 18:07:59 +0000
  • e74dbc3377 back.pysim: support async reset. whitequark 2019-01-26 18:07:43 +0000
  • 8686e9aa06 back.pysim: give better names to unnamed fragments and their signals. whitequark 2019-01-26 18:07:16 +0000
  • 7acea8f3ce examples: update for newer API. whitequark 2019-01-26 16:25:05 +0000
  • b133eb735f back.rtlil: accept any elaboratable, not just fragments. whitequark 2019-01-26 16:11:29 +0000
  • 4bf80a6e33 compat: suppress deprecation warnings that are internal or during test. whitequark 2019-01-26 15:43:00 +0000
  • 7890c0adc8 test.compat: reenable tests converting to Verilog. whitequark 2019-01-26 15:29:09 +0000
  • 4887771e4a compat.sim: fix deprecated stdlib import. whitequark 2019-01-26 15:26:54 +0000
  • 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). whitequark 2019-01-26 02:31:12 +0000
  • 4922a73c5d test.compat: import tests from Migen as appropriate. whitequark 2018-12-18 18:05:37 +0000
  • f71e0fffbb hdl.ast: fix shape calculation for *. whitequark 2019-01-26 00:54:02 +0000
  • 7b25665fde back.pysim: fix behavior of initial cycle for sync processes. whitequark 2019-01-22 17:51:44 +0000
  • 1782b841b2 lib.fifo: in FIFOInterface.read(), check readable on the right cycle. whitequark 2019-01-22 07:03:46 +0000
  • eeb023a7f5 compat.genlib.fifo: adjust _FIFOInterface shim to not require fwft=. whitequark 2019-01-22 06:56:46 +0000
  • 2c80f35de4 lib.fifo: fix typo in AsyncFIFO documentation. whitequark 2019-01-22 05:47:50 +0000
  • e33580cf4c lib.fifo: add AsyncFIFO and AsyncFIFOBuffered. whitequark 2019-01-21 16:02:46 +0000
  • 12e04e4ee5 back.pysim: wake up processes before ever committing any values. whitequark 2019-01-21 16:00:25 +0000
  • 52a9f818f1 compat.genlib.cdc: add missing import. whitequark 2019-01-20 03:03:48 +0000
  • c110fe6a9d compat.genlib.cdc: add GrayCounter and GrayDecoder shims. whitequark 2019-01-20 02:29:08 +0000
  • b6cff2c098 lib.coding: add GrayEncoder and GrayDecoder. whitequark 2019-01-20 02:20:34 +0000
  • 9757157fe2 lib.coding: add width as attribute to all coders. whitequark 2019-01-20 01:59:09 +0000
  • 9de9272709 lib.fifo: use memory in the FIFO model. whitequark 2019-01-19 09:27:13 +0000
  • 6ea0a12dd4 lib.fifo: use model equivalence to simplify formal specification. whitequark 2019-01-19 08:57:18 +0000
  • 38b3c4af31 hdl.ast: implement shape for modulo operator. whitequark 2019-01-19 09:26:26 +0000
  • 5e2b46f727 hdl.ast: add Value.implies. whitequark 2019-01-19 08:56:44 +0000
  • c5d67b0461 hdl.xfrm: mark internal registers used in lowering Sample(). whitequark 2019-01-19 06:02:04 +0000
  • 94b23dd2c8 doc: update COMPAT_SUMMARY. whitequark 2019-01-19 01:01:32 +0000
  • e3b5b2acc8 fhdl.specials: add compatibility shim for Tristate. whitequark 2019-01-19 02:19:06 +0000
  • 3ed519383c lib.fifo: fix simulation read/write methods to take only one cycle. whitequark 2019-01-19 01:37:58 +0000
  • 45088f7824 compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered. whitequark 2019-01-19 01:06:27 +0000
  • 97b990272e lib.fifo: formally verify FIFO contract. whitequark 2019-01-19 00:52:56 +0000
  • b50b47d984 hdl.ast: give Assert and Assume their own src_loc. whitequark 2019-01-19 00:08:51 +0000
  • 66466a8a0e back.rtlil: only emit each AnyConst/AnySeq cell once. whitequark 2019-01-18 01:27:17 +0000
  • 60089db075 cli: add missing default for generate Alain Péteut 2019-01-17 21:32:47 +0100
  • 5a831ce31c lib.fifo: add basic formal specification. whitequark 2019-01-17 05:26:54 +0000
  • fa8e876356 hdl.ast: allow sampling ClockSignal, ResetSignal. whitequark 2019-01-17 05:23:06 +0000
  • 8c96675580 hdl.ast: add Past, Stable, Rose, Fell. whitequark 2019-01-17 04:31:27 +0000
  • 16f90d3585 formal: extract from toplevel module. whitequark 2019-01-17 01:43:07 +0000
  • 198efcad31 hdl.xfrm: add SampleLowerer. whitequark 2019-01-17 01:41:02 +0000
  • b3de114d67 hdl.ast: add Sample. whitequark 2019-01-17 01:36:27 +0000
  • b78a2be9f6 lib.fifo: port sync FIFO queues from Migen. whitequark 2019-01-16 17:19:46 +0000
  • cb2f18ee37 hdl.ast: fix naming of Signal.like() signals when tracer fails. whitequark 2019-01-16 15:55:28 +0000
  • f2425001aa back.rtlil: slightly nicer naming for $next signals. NFC. whitequark 2019-01-16 17:20:30 +0000
  • 935bf2d8cf back.rtlil: rename \sig$next to $next$sig. whitequark 2019-01-16 14:51:20 +0000
  • bfe246a127 Travis: install SymbiYosys and Yices2. whitequark 2019-01-16 00:57:09 +0000
  • 6191760c30 Unbreak 655d02d5. whitequark 2019-01-15 23:09:10 +0000
  • 655d02d5b8 back.rtlil: Generate $anyconst and $anyseq cells. William D. Jones 2019-01-15 16:06:19 -0500
  • 77728c2dea hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children. William D. Jones 2019-01-15 16:05:25 -0500
  • 6fdbc3d885 hdl.ast: Add AnyConst and AnySeq value types. William D. Jones 2019-01-15 15:13:47 -0500
  • 1880686e2e README: add LambdaConcept sponsorship Sebastien Bourdeauducq 2019-01-15 15:58:38 +0800
  • c4276f7cf7 lib.io: pass pin to platform.get_tristate(). whitequark 2019-01-14 21:39:19 +0000
  • b534e92dd5 hdl.ir: allow explicitly requesting flattening. whitequark 2019-01-14 17:04:23 +0000
  • 6f66885c09 lib.io: lower to platform-independent tristate buffer. whitequark 2019-01-14 16:50:04 +0000
  • 011bf2258e hdl: make ClockSignal and ResetSignal usable on LHS. whitequark 2019-01-14 15:38:16 +0000
  • 664b4bcb3a hdl.dsl: cases wider than switch test value are unreachable. whitequark 2019-01-13 08:51:49 +0000
  • 3083c1d6dd hdl.dsl: accept (but warn on) cases wider than switch test value. whitequark 2019-01-13 08:46:28 +0000
  • cbf7bd6e31 back.pysim: handle non-driven, non-port signals. whitequark 2019-01-13 08:31:38 +0000
  • 06faeee357 back.verilog: better error message if Yosys is not found. whitequark 2019-01-13 08:10:23 +0000
  • 307de722cb back.verilog: remove undriven check. whitequark 2019-01-08 20:42:56 +0000
  • 560bb007cc Give the top level scope a name to fix VCD hierarchy. Adam Greig 2019-01-06 00:10:37 +0000
  • a2b04d71d0 hdl.ast: allow slicing [n:n] into n-bit value. whitequark 2019-01-02 18:14:57 +0000
  • ef1e0b8d55 back.rtlil: translate empty slices correctly. whitequark 2019-01-02 18:14:29 +0000
  • f31055a4ef back.rtlil: Generate RTLIL for Assert/Assume statements. William D. Jones 2019-01-01 01:31:54 -0500
  • f77dc40256 hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children. William D. Jones 2018-12-30 05:17:39 -0500
  • 2412650f56 hdl.dsl: Support Assert and Assume where an Assign can occur. William D. Jones 2018-12-28 02:10:15 -0500
  • e6517a33c7 hdl.ast: Add Assert and Assign statements. William D. Jones 2018-12-28 01:33:19 -0500
  • ea7e19ed5c hdl.ast: experimentally add Value._as_const. whitequark 2019-01-01 09:50:39 +0000
  • 1a9dcd2f28 back.rtlil: fix typo. whitequark 2019-01-01 08:50:28 +0000
  • 3c07d8d52c hdl.rec: include record name in error message. whitequark 2019-01-01 03:39:12 +0000
  • 031a9e2616 hdl.rec: use a helpful error on unknown field reference. whitequark 2019-01-01 03:35:34 +0000
  • d78e6c155b hdl.mem: add DummyPort, for testing and verification. whitequark 2019-01-01 03:08:10 +0000
  • ae3c5834ed back.rtlil: match shape of Array elements to ArrayProxy shape. whitequark 2018-12-31 03:43:34 +0000
  • cdc40eaa9b back.rtlil: fix typo. whitequark 2018-12-31 03:37:38 +0000
  • 39eb2e8fa7 lib.cdc: fix tests to actually run. whitequark 2018-12-29 15:02:44 +0000
  • 849c649259 back.pysim: warn if simulation is not run. whitequark 2018-12-29 15:02:04 +0000
  • 92a96e1644 hdl.rec: add basic record support. whitequark 2018-12-28 13:22:10 +0000
  • d66bbb0df8 tracer: factor out get_src_loc(). whitequark 2018-12-28 01:31:24 +0000
  • 3ea35b8566 lib.coding: fix tests to actually run, and fix code to fix tests. whitequark 2018-12-27 21:45:55 +0000
  • 470d66934f hdl.dsl: add support for fsm.ongoing(). whitequark 2018-12-27 16:02:31 +0000
  • de50ccec90 hdl.mem: add missing __all__. whitequark 2018-12-26 17:15:54 +0000