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• 39a83f4d99 setup: fix documentation URL for releases. Catherine 2021-12-16 18:02:11 +0000
• e2b3e8caf9 CI: publish documentation at https://amaranth-lang.org/docs/amaranth/ Catherine 2021-12-16 17:44:02 +0000
• a243e0443e CI: publish documentation for tagged commits. Catherine 2021-12-16 17:09:45 +0000
• e156ac62c5 docs: don't call Python modules "packages". Catherine 2021-12-16 15:44:08 +0000
• 538c14116c sim.pysim: use "bench" as a top level root for testbench signals. Irides 2021-12-15 19:47:48 -0600
• 810c19dde4 Revert "Add PEP 518 pyproject.toml." Catherine 2021-12-16 15:00:51 +0000
• 22c7453783 Revert "setup: add workaround for pypa/pip#7953." Catherine 2021-12-16 15:00:21 +0000
• 55756e9568
  examples/uart: acknowledging RX data should deassert RX ready. Ben Newhouse 2021-12-16 08:31:32 -0500
• 0169d47365 docs/changes: add simulation-related changes. Catherine 2021-12-16 08:03:53 +0000
• b1f5664b05 setup: add workaround for pypa/pip#7953. Irides 2021-12-14 08:56:58 -0600
• 847e46927b back.{verilog,rtlil}: fix commit d83c4a1b. Catherine 2021-12-14 10:47:04 +0000
• a6a13dd612 docs: add changelog. Catherine 2021-12-13 06:40:55 +0000
• d83c4a1b21 back.{rtlil,verilog}: deprecate implicit ports. Irides 2021-12-13 06:02:29 -0600
• 24c4da2b2f lib.fifo: clarify AsyncFIFO{,Buffered}.r_rst documentation. NFC. Catherine 2021-12-13 09:53:29 +0000
• 47c79cf3c8 docs: simplify. NFC. Catherine 2021-12-13 09:03:22 +0000
• 40b92965c9 docs: cover amaranth.vendor. Irides 2021-12-13 03:10:40 -0600
• 1ee2482c6b sim: represent time internally as 1ps units modwizcode 2021-12-12 21:43:20 -0600
• fab9fb1fea Revert "CI: add CPython 3.11 to the build matrix." Catherine 2021-12-13 07:58:01 +0000
• 6860a0629a CI: add CPython 3.11 to the build matrix. Catherine 2021-12-13 07:55:46 +0000
• d2c569c45e docs: cover amaranth.lib.fifo. modwizcode 2021-12-13 00:38:30 -0600
• 2adbe59e4f docs: formatting and readability improvements. Catherine 2021-12-13 06:33:36 +0000
• 18837b9029 docs: cover amaranth.lib.cdc. Catherine 2021-12-13 06:23:12 +0000
• 3a8cd63b23 docs: cover amaranth.lib.coding. Catherine 2021-12-13 05:48:31 +0000
• 25163364d8 README: point IRC link to web.libera.chat. Catherine 2021-12-13 02:18:54 +0000
• 0b74d1c5f6 back.rtlil: support slicing on Parts Irides 2021-12-11 10:27:12 -0600
• 7c161957bf build.dsl: check type of resource number. whitequark 2021-12-11 13:37:15 +0000
• 7e2b72826f sim.core: warn when driving a clock domain not in the simulation. whitequark 2021-12-11 13:22:24 +0000
• ac13a5b3c9 sim._pyrtl: reject very large values. whitequark 2021-12-11 13:00:46 +0000
• 599615ee3a hdl.ir: reject elaboratables that elaborate to themselves. whitequark 2021-12-11 12:39:34 +0000
• 90777a65c8 build.plat,vendor: add missing compatibility shims for NMIGEN_ENV_*. whitequark 2021-12-11 11:49:47 +0000
• b1eba5fd82 vendor.xilinx: support setting options on synth_design Closes #606. Irides 2021-12-11 06:02:39 -0600
• fd7d01ef10 back.rtlil,cli: allow suppressing generation of src attributes. whitequark 2021-12-11 11:38:40 +0000
• 66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names. whitequark 2021-12-11 11:12:25 +0000
• b452e0e871 hdl.ast: support division and modulo with negative divisor. whitequark 2021-12-11 08:52:14 +0000
• 25573c5eff back.rtlil: extend unsigned operand of binop if another is signed. whitequark 2021-12-11 10:25:41 +0000
• 44b8bd29af hdl.ast: warn on bare integer value used in Cat()/Repl(). whitequark 2021-12-11 08:18:33 +0000
• de7c9acb19 _utils: don't crash trying to flatten() strings. whitequark 2021-12-11 07:39:35 +0000
• 0fb2b4cd39 docs: fix download link in start.rst. whitequark 2021-12-11 06:32:32 +0000
• 116d4b9bc2 nmigen.cli: add missing imports. whitequark 2021-12-10 17:16:32 +0000
• 4d83e13103 CI: fix test discovery command. whitequark 2021-12-10 10:48:14 +0000
• a7fdf661cf CI: only discover tests under tests/. whitequark 2021-12-10 10:45:05 +0000
• e11d033b0f README: update header. whitequark 2021-12-10 10:42:15 +0000
• 909a3b8be7 Rename nMigen to Amaranth HDL. whitequark 2021-12-10 05:39:50 +0000
• 0b28a97ca0 CI: preserve YoWASP cache as well. whitequark 2021-10-08 17:48:00 +0000
• e91a5ad934 _toolchain.cxx: ignore another deprecation warning (on Python 3.10). whitequark 2021-10-08 17:48:00 +0000
• 3379f072a0 _toolchain.cxx: ignore deprecation warning (on Python 3.6). whitequark 2021-10-08 17:48:00 +0000
• 369cc59d69 docs: update requirements. whitequark 2021-10-08 17:48:00 +0000
• 8081df1265 _toolchain.cxx: use distutils from setuptools. whitequark 2021-10-08 17:48:00 +0000
• 97aa7a3aa9 vendor.xilinx_*: deprecate legacy Xilinx platform aliases. whitequark 2021-10-08 17:48:00 +0000
• f0af0a8449 Run tests on Python 3.10. whitequark 2021-10-08 17:48:00 +0000
• 7c740a85ea Simplify CI workflow. whitequark 2021-10-08 17:48:00 +0000
• a2ef4cb6b8 Add PEP 518 pyproject.toml. whitequark 2021-10-08 17:48:00 +0000
• 177f1b2e40
  vendor.intel: add Mistral toolchain support. Olivier Galibert 2021-10-14 18:02:22 +0200
• 11914a1e67 hdl.ast: improve interaction of ValueCastable with custom __getattr__. whitequark 2021-10-03 20:28:07 +0000
• fac1b4b2d1 hdl.dsl: simplify. NFC. whitequark 2021-10-02 17:00:01 +0000
• e88d283ed3 hdl.ast: simplify Mux implementation. whitequark 2021-10-02 14:18:02 +0000
• 65499d5c45 hdl.ast: add tests for casting bare integers in {Cat,Repl}. whitequark 2021-10-02 13:18:11 +0000
• 9f78ac0691
  hdl.ast: remove quadratic time complexity in Statement.cast(). Anton Blanchard 2021-09-27 11:00:56 +1000
• 9834b7e95f
  vendor.xilinx: avoid using / for hierarchy in ISE constraint files. H-S-S-11 2021-09-25 11:41:23 +0100
• bdbe8bff27 Unify Xilinx platforms into a single class, support more devices Marcelina Kościelnicka 2020-12-16 16:35:57 +0100
• da8a492be7 _toolchain: Properly set compiler/linker executables on Gentoo Adam Jeliński 2021-09-21 10:33:26 +0200
• 23a44f3cb6 vendor.xilinx_{7series,ultrascale}: hierachical -> hierarchical Robin Ole Heinemann 2021-08-16 23:31:57 +0200
• abb2642256 _toolchain: substitute '+' with 'X' in tool_env_var(). Jean-François Nguyen 2021-07-16 19:16:56 +0200
• e974a31022
  README: update IRC channel. whitequark 2021-05-20 03:07:51 +0000
• 78be9e7b67 rpc: fix parsing of negative signed parameters Robin Ole Heinemann 2021-05-18 20:43:16 +0200
• b38b2cdad7 test.test_hdl_ast.OperatorTestCase: remove duplicate test_bool Robin Ole Heinemann 2021-05-18 21:18:51 +0200
• 2d85f888d6 tests: rename tests with duplicate names Robin Ole Heinemann 2021-05-18 21:18:14 +0200
• b93a54ac58 tests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix Robin Ole Heinemann 2021-05-18 21:15:02 +0200
• f570e1bbeb *: remove unused variables Robin Ole Heinemann 2021-05-18 21:10:47 +0200
• 25caf4045b *: remove unused imports Robin Ole Heinemann 2021-05-18 20:39:57 +0200
• d09dedfb48 tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements Thomas Watson 2021-05-10 21:02:29 -0500
• 7443f89200 hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements Thomas Watson 2021-05-10 20:59:34 -0500
• d824795c2c
  vendor.lattice_{ecp5,machxo_2_3l}: remove -forceAll from Diamond scripts. Adam Greig 2021-04-12 10:48:20 +0100
• c84d4aff6e CI: fix sri-csl/formal-methods PPA series. whitequark 2021-03-18 23:56:52 +0000
• c30dcea24d hdl.ast: handle int subclasses as slice start/stop values. whitequark 2021-03-18 23:52:23 +0000
• f7c2b9419f compat.genlib.roundrobin: fix missing imports dx-mon 2021-02-04 03:10:44 +0000
• 746886ca8a
  vendor.xilinx_7series: fix tool names for symbiflow. nickoe 2021-01-31 19:08:44 +0100
• 09de190bd1 vendor.lattice_ecp5: correctly generate OE signaling when xdr=0 Katherine Temkin 2021-01-25 08:41:45 -0700
• 6ce2b21e19
  vendor.lattice_ecp5: replicate OE signal for each output bit. Adam Greig 2021-01-23 18:06:52 +0000
• a2da34a5bc README: add ChipEleven as a sponsor. whitequark 2021-01-23 03:26:42 +0000
• 490fca5745 docs: Update up_counter to avoid deprecation warning Joel Stanley 2021-01-15 13:28:21 +1030
• 3a4b61c16e
  vendor.lattice_ecp5: remove outdated comment in ECP5 platform. Adam Greig 2021-01-14 11:34:03 +0000
• 9af8201727 lib.fifo.AsyncFIFOBuffered: fix output register accounting Robin Ole Heinemann 2021-01-03 00:17:48 +0100
• 2a7a3aef87 lib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency Robin Ole Heinemann 2021-01-03 00:14:26 +0100
• d15705cf4f lib.fifo: use proper clock domains in AsyncFIFO tests Robin Ole Heinemann 2021-01-03 00:13:46 +0100
• 76efe862fa lib.fifo.AsyncFIFOBuffered: use FFSynchronizer instead of AsyncFFsynchronizer Robin Ole Heinemann 2021-01-03 00:12:31 +0100
• b466b724fe Revert "vendor.xilinx_7series: byte swap generated bitstream" whitequark 2020-12-12 22:08:57 +0000
• 7dde2aac7c hdl.ast: formatting. NFC. whitequark 2020-12-12 14:11:40 +0000
• 818c8bc464 hdl.ast: normalize case values to two's complement, not signed binary. whitequark 2020-12-12 12:42:12 +0000
• 4e7e0b33d5 back.rtlil: give private items an appropriate name. NFCI. whitequark 2020-12-12 12:18:59 +0000
• 59ef6e6a1c build.plat: make verbose work like all other overrides. whitequark 2020-11-24 23:07:09 +0000
• 90e3504097 vendor.intel: implement add_settings (QSF) and add_constraints (SDC) overrides. whitequark 2020-11-24 20:35:58 +0000
• f1473e483a vendor.xilinx_spartan_3_6: fix typo. whitequark 2020-11-22 00:16:02 +0000
• 39ff7203ba hdl.ast: remove dead code. NFC. whitequark 2020-11-21 17:29:55 +0000
• c1ed90807b
  nmigen.hdl.rec: restore Record.shape(). awygle 2020-11-17 11:36:58 -0800
• 44318149e0
  sim._pyrtl: mask Mux selection operand. Marcelina Kościelnicka 2020-11-14 16:22:34 +0100
• adef3b2e7b vendor.quicklogic: enable SoC clock configuration Jan Kowalewski 2020-11-13 13:58:11 +0100
• 36bc1d2b4d vendor.quicklogic: write OpenOCD scripts as part of build process. whitequark 2020-11-13 05:44:16 +0000
• d6da4c257b build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files. whitequark 2020-11-10 05:30:21 +0000
• ea94c9cc45
  hdl.rec: proxy operators correctly. awygle 2020-11-09 12:20:25 -0800