whitequark
1eee7cd76f
lib.io: allow dir="oe".
...
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.
E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
2019-06-03 04:28:53 +00:00
whitequark
9ba2efd86b
build.{res,plat}: use xdr=0 as default, not xdr=1.
...
The previous behavior was semantically incorrect.
2019-06-03 03:36:32 +00:00
whitequark
cd6488c782
build.res: allow requesting raw ports, with dir="-".
...
This provides an escape hatch for the case where the nMigen platform
code is not flexible enough, and a IO buffer primitive needs to be
instantiated directly.
2019-06-03 03:36:32 +00:00
whitequark
c30617fc05
lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer.
2019-06-03 03:36:32 +00:00
whitequark
3327deae92
vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.
2019-06-03 03:01:56 +00:00
whitequark
f417725b10
build.res: if not specified, request resource #0 .
...
This markedly differs from oMigen system, which would request
consecutive resources. The difference is deliberate; most resources
are singular, so it does not matter for them, and for resources where
it does matter, which pins are requested should not depend on order
of execution of `platform.request`.
2019-06-03 02:54:17 +00:00
whitequark
dc17d06fe9
vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.
...
The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
2019-06-03 02:51:59 +00:00
whitequark
c6a0761b3a
hdl.ir: accept LHS signals like slices as Instance io ports.
...
This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
2019-06-03 02:39:14 +00:00
whitequark
b8a61edc2f
hdl.dsl: allow adding submodules with computed name, like with domains.
2019-06-03 02:22:55 +00:00
whitequark
b64a31255c
hdl.ir: accept expanded (kind, name, value) tuples in Instance.
...
This is useful for e.g. programmatically generating parameters
without having to mess with kwargs dicts.
2019-06-03 02:12:01 +00:00
whitequark
fb01854372
build.{res,plat}: propagate extras to pin fragment factories.
...
This is necessary because on some platforms, like iCE40, extras
become parameters on an IO primitive, since the constraint file
format is not expressive enough for all of them.
2019-06-03 01:58:43 +00:00
whitequark
268fe6330e
build.res: simplify. NFC.
2019-06-03 01:29:20 +00:00
whitequark
98497b2075
build.dsl: require a dict for extras instead of a stringly array.
...
Fixes #72 .
2019-06-02 23:36:21 +00:00
whitequark
e4ebe03115
vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles.
2019-06-02 04:12:50 +00:00
whitequark
37152c733e
vendor.tinyfpga_{b→bx}
2019-06-02 04:11:28 +00:00
whitequark
bff08c5016
vendor.tinyfpga_b: fix IO_STANDARD.
2019-06-02 04:04:07 +00:00
Simon Kirkby
358b98e5de
vendor.tinyfpga_b: implement.
2019-06-02 01:20:09 +00:00
whitequark
39fad9a955
vendor.icestick: fix typo.
2019-06-02 01:13:03 +00:00
whitequark
ba0fcddb2c
vendor.ice40_hx1k_blink_evn: implement.
2019-06-01 16:48:07 +00:00
whitequark
eab372383a
vendor.icestick: implement.
2019-06-01 16:47:20 +00:00
whitequark
321d245e95
vendor.fpga.lattice_ice40: implement.
2019-06-01 16:47:01 +00:00
whitequark
b1eab9fb3b
build.plat: implement.
2019-06-01 16:43:27 +00:00
whitequark
53ddff9f33
build.res: always return a Pin record.
...
In the simple cases, a Pin record consisting of exactly one field
is equivalent in every way to this single field. In the more complex
case however, it can be used as a record, making the code more robust
such that it works with both bidirectional and unidirectional pins.
2019-06-01 16:41:30 +00:00
whitequark
8c1b5a26b3
build.res: accept a list of clocks in ConstraintManager constructor.
2019-06-01 15:41:41 +00:00
whitequark
f17375a60b
back.rtlil: allow specifying platform for convert().
2019-05-26 17:10:56 +00:00
whitequark
578dba263f
Add versioneer.
2019-05-26 11:20:13 +00:00
whitequark
b0ba960296
hdl.ir: silence unused elaboratable warning on interpreter crash.
2019-05-26 10:48:39 +00:00
Jean-François Nguyen
d393c5ec64
build.res: add ConstraintManager.
2019-05-26 01:26:58 +00:00
whitequark
3a9fe31133
build.dsl: make Pins and DiffPairs iterable.
...
Returns pin names.
2019-05-25 22:43:48 +00:00
whitequark
48145cee02
build.dsl: improve repr of Pins() and DiffPairs().
2019-05-25 22:43:23 +00:00
whitequark
2b7dc37ffe
hdl.rec: allow providing fields during construction.
...
This allows creating records populated with e.g. signals with custom
names, or sub-records that are instances of Record subclasses.
2019-05-25 22:06:56 +00:00
whitequark
3392708e2b
Consider Instances a part of containing fragment for use-def purposes.
...
Fixes #70 .
2019-05-25 20:13:43 +00:00
Chris Osterwood
699fe5a675
Add import so that Tristate.elaborate builds
2019-05-20 16:34:31 +00:00
whitequark
c337246fc5
hdl.ir: when adding sync domain to a design, also add it to ports.
...
Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.
Fixes #67 .
2019-05-15 06:44:50 +00:00
whitequark
39bc59c924
hdl.ir: during port propagation, defs should take priority over uses.
2019-05-13 15:34:13 +00:00
whitequark
921f506e69
back.rtlil: assign undriven signals to their reset value.
...
Fixes #35 .
2019-05-13 08:33:55 +00:00
whitequark
744e33f42d
hdl: make all public Value classes other than Record final.
...
In some cases, nMigen uses type() instead of isinstance() to dispatch
on types. Make sure all such uses of type() are robust; in addition,
make it clear that nMigen AST classes are not meant to be subclassed.
(Record is an exception.)
Fixes #65 .
2019-05-12 05:40:17 +00:00
whitequark
958cb18b88
hdl.ir: only pull explicitly specified ports to toplevel, if any.
...
Fixes #30 .
2019-05-12 05:21:23 +00:00
Jean-François Nguyen
6a77122c2e
lib.io: add a name argument to the Pin constructor.
2019-04-24 22:02:20 +00:00
whitequark
a982fbe377
build.dsl: style. NFC.
2019-04-24 15:02:30 +00:00
Jean-François Nguyen
dd5bd1c88d
build: add DSL for defining platform resources.
2019-04-24 11:49:01 +00:00
whitequark
97af266645
back.verilog: allow stripping the src attribute, for cleaner output.
2019-04-22 14:59:53 +00:00
Alain Péteut
c8e92c0612
compat.fhdl.specials: fix Tristate, TSTriple.
...
* fix TSTriple instance.
* TSTriple, Tristate: tag as Elaboratable
2019-04-22 09:57:12 +00:00
Alain Péteut
371dc8bebe
compat.fhdl.specials: fix Tristate.
2019-04-22 08:49:08 +00:00
whitequark
93d15abcf1
compat.fhdl.specials: fix TSTriple.
2019-04-22 08:15:03 +00:00
whitequark
585514e6ed
hdl.ir: rework named port handling for Instances.
...
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.
While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
2019-04-22 07:46:47 +00:00
whitequark
44711b7d08
hdl.ir: detect elaboratables that are created but not used.
...
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.
Fixes #3 .
2019-04-21 08:52:57 +00:00
whitequark
85ae99c1b4
back.rtlil: emit nmigen.hierarchy attribute.
...
Fixes #54 .
2019-04-21 07:55:08 +00:00
whitequark
360bc9b5b4
hdl.ast: improve tests for exceptional conditions.
2019-04-21 07:20:00 +00:00
whitequark
33f9bd2a1d
hdl.ast: accept Signals with identical min/max bounds.
...
And produce a 0-bit signal.
Fixes #58 .
2019-04-21 07:16:59 +00:00
