Commit graph

178 commits

Author SHA1 Message Date
whitequark b227352258 hdl.ast: cast Mux() selector to bool if it is not a 1-bit value.
Fixes #232.
2019-09-23 13:39:31 +00:00
whitequark bc53bbf564 hdl.mem,lib.fifo: use keyword-only arguments for memory geometry.
Fixes #230.
2019-09-23 12:15:06 +00:00
whitequark 1aeb11d7e3 hdl.mem: simplify. NFC. 2019-09-23 11:16:29 +00:00
whitequark 649444449d hdl.ast: make Signal(name=) a keyword-only argument.
Almost no code would specify Signal(_, name) as a positional argument
on purpose, but forgetting parens and accidentally placing signedness
into the name position is so common that we had a test for it.
2019-09-23 11:08:43 +00:00
whitequark 1976310bf0 hdl.rec: fix using Enum subclass as shape if direction is specified.
Also improves error messages.

Fixes #224.
2019-09-22 17:23:32 +00:00
whitequark 4c582ef609 hdl.rec: allow using Enum subclass as shape.
Fixes #223.
2019-09-22 15:17:40 +00:00
whitequark a13a21cbd6 hdl.ast: update docs. NFC. 2019-09-21 06:53:13 +00:00
whitequark 4b3a068b15 hdl.mem: use 1 as reset value for ReadPort.en.
This is necessary for consistency, since for transparent read ports,
we currently do not support .en at all (it is fixed at 1) due to
YosysHQ/yosys#760. Before this commit, changing port transparency
would require adding or removing an assignment to .en, which is
confusing and error-prone.

Also, most read ports are always enabled, so this behavior is also
convenient.
2019-09-20 19:51:13 +00:00
whitequark 378e924280 hdl.ast: rename nbits to width.
Also, replace `bits, sign = x.shape()` with more idiomatic
`width, signed = x.shape()`.

This unifies all properties corresponding to `len(x)` to `x.width`.
(Not all values have a `width` property.)

Fixes #210.
2019-09-20 15:36:25 +00:00
whitequark 4777a7b3a2 hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns.
Fixes #207.
2019-09-16 19:22:12 +00:00
whitequark e8f79c5539 hdl.ast: add Value.matches(), accepting same language as Case().
Fixes #202.
2019-09-14 21:06:12 +00:00
whitequark f292a1977c hdl.dsl: improve error messages for Case(). 2019-09-14 20:58:19 +00:00
whitequark 32310aecad hdl.ast: add Value.xor, mapping to $reduce_xor.
Fixes #147.
2019-09-13 14:29:46 +00:00
whitequark b23a9794a4 hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}.
Refs #147.
2019-09-13 13:14:52 +00:00
whitequark 42805ad959 hdl.mem: use keyword-only arguments as appropriate. 2019-09-12 20:03:48 +00:00
whitequark 7342662bee hdl.ast: warn if reset value is truncated.
Fixes #183.
2019-09-10 07:26:34 +00:00
whitequark 9b398b502e hdl.ast: check type of Sample(domain=...).
Fixes #199.
2019-09-08 23:55:05 +00:00
whitequark 3f6abc0b7a hdl.dsl: add Default(), an alias for Case() with no arguments.
Fixes #197.
2019-09-08 12:24:18 +00:00
whitequark eb04a2509e hdl.mem,lib,examples: use Signal.range(). 2019-09-08 12:19:13 +00:00
whitequark ccfbccc044 hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...).
Fixes #196.
2019-09-08 12:10:31 +00:00
whitequark 943ce317af hdl.ast,back.rtlil: implement Cover.
Fixes #194.
2019-09-03 01:32:24 +00:00
whitequark 2e20622046 hdl.cd: add negedge clock domains.
Fixes #185.
2019-08-31 22:05:48 +00:00
whitequark 13316053e3 build.plat, hdl.ir: coordinate missing domain creation.
Platform.prepare() was completely broken after addition of local
clock domains, and only really worked before by a series of
accidents because there was a circular dependency between creation
of missing domains, fragment preparation, and insertion of pin
subfragments.

This commit untangles the dependency by adding a separate public
method Fragment.create_missing_domains(), used in build.plat.

It also makes DomainCollector consider both used and defined domains,
such that it will work on fragments before domain propagation, since
create_missing_domains() can be called by user code before prepare().

The fragment driving missing clock domain is not flattened anymore,
because flattening does not work well combined with local domains.
2019-08-19 22:52:01 +00:00
whitequark 003ba3b45f hdl.cd: implement local clock domains.
Closes #175.
2019-08-19 21:44:33 +00:00
whitequark 69d36dc139 hdl.xfrm: lower resets in DomainLowerer as well.
Changed in preparation for introducing local clock domains.

Also makes elaboration about 15% faster.
2019-08-19 21:44:30 +00:00
whitequark 404f99f022 hdl.xfrm: consider fragment's own domains in DomainLowerer.
Changed in preparation for introducing local clock domains.
2019-08-19 21:07:02 +00:00
whitequark 32bfbb11cb formal→asserts
Closes #171.
2019-08-19 20:23:24 +00:00
whitequark d44ea4e9fe hdl.xfrm: make deprecated CEInserter more well-behaved. 2019-08-18 16:26:45 +00:00
whitequark ed7e07c6c1 hdl.ast: implement Initial.
This is the last remaining part for first-class formal support.
2019-08-15 02:53:07 +00:00
whitequark 40abaef858 hdl.xfrm: sample cache should be per-fragment. 2019-08-15 02:45:31 +00:00
whitequark fa0fa056ba hdl.xfrm: CEInserter→EnableInserter.
Fixes #166.
2019-08-12 13:39:26 +00:00
whitequark 9d2cbbabb8 hdl.ast: hash-cons ValueKey.
This speeds up elaboration by ~10%.
2019-08-08 10:56:53 +00:00
whitequark 99d205494a hdl.dsl: reword m.If(~True) warning to be more clear.
Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.
2019-08-03 18:52:24 +00:00
whitequark e0b54b417e hdl.ir: allow adding more than one domain in missing domain callback.
This is useful for injecting complex power-on reset logic.
2019-08-03 18:19:40 +00:00
whitequark 9c28b61d9f hdl.ir: don't expose as ports missing domains added via elaboratables.
The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
2019-08-03 16:39:21 +00:00
whitequark cea92e9531 hdl.ir: allow returning elaboratables from missing domain callback.
This allows e.g. injecting a clock/reset generator in platform build
code on demand (i.e. if the domain is not instantiated manually).

See #57.
2019-08-03 15:44:02 +00:00
whitequark fc846532c7 hdl.ir: raise DomainError if a domain is used but not defined.
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
2019-08-03 15:31:24 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing.
See #57.
2019-08-03 14:54:20 +00:00
whitequark ace2b5ff0a hdl.dsl: warn on suspicious statements like m.If(~True):.
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.

Fixes #159.
2019-08-03 14:00:29 +00:00
whitequark 0a603b3844 hdl.ast: fix typo. 2019-08-03 13:21:09 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select.
Fixes #148.
2019-08-03 13:07:06 +00:00
whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires.
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.

Also fixes incorrect source location on value.part().
2019-08-03 12:51:57 +00:00
whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None.
Fixes #164.
2019-08-03 12:30:39 +00:00
whitequark 995e4adb8c hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.
Fixes #154.
2019-07-31 05:20:05 +00:00
N. Engelhardt 698b005182 hdl.dsl: add getters to m.submodules. 2019-07-19 12:39:47 +00:00
whitequark 2fa858b003 hdl.ir: make UnusedElaboratable a real warning.
Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.
2019-07-10 12:46:54 +00:00
whitequark 00c5209a47 hdl.{ast,dsl},back.rtlil: track source locations for switch cases.
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.
2019-07-09 19:26:47 +00:00
whitequark 0ab0a74ec1 hdl.rec: respect modifications to signals in Record.like().
Fixes #126.
2019-07-08 10:59:15 +00:00
whitequark a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
Fixes #125.
2019-07-08 10:26:49 +00:00
whitequark ec7fcd3697 hdl.xfrm: don't overwrite source locations on ClockDomain signals.
On the sample of examples/basic/*.py, there are no remaining
incorrectly inferred locations.
2019-07-08 09:58:12 +00:00