whitequark
287a0531b3
lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin.
2019-04-15 16:27:23 +00:00
whitequark
0a2a7025a6
hdl.xfrm: allow using FragmentTransformer on any elaboratable.
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Fixes #29 .
2019-04-10 00:23:11 +00:00
whitequark
a74cacdc69
hdl.ast: handle a common typo, such as Signal(1, True).
2019-04-03 14:59:01 +00:00
whitequark
c9c9307a5e
test_sim: add missing add_process().
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Fixes #43 .
2019-03-28 17:50:14 +00:00
anuejn
3c95299c4e
hdl.rec: separate record and signal name with __, not _.
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This makes names of signals within records less ambiguous, in case
they themselves have underscores within them.
2019-03-25 14:26:00 +00:00
whitequark
8ee6bd80ff
hdl.ir: raise a more descriptive error on non-elaboratable object.
2019-02-14 20:52:42 +00:00
whitequark
f44ca291c1
lib.cdc: add ResetSynchronizer.
2019-01-26 18:07:59 +00:00
whitequark
4bf80a6e33
compat: suppress deprecation warnings that are internal or during test.
2019-01-26 15:43:00 +00:00
whitequark
7890c0adc8
test.compat: reenable tests converting to Verilog.
2019-01-26 15:29:09 +00:00
whitequark
4948162f33
hdl.ir: rename .get_fragment() to .elaborate().
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Closes #9 .
2019-01-26 02:31:12 +00:00
whitequark
4922a73c5d
test.compat: import tests from Migen as appropriate.
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test_signed and test_coding are adjusted slightly to account for
differences in comb propagation between the simulators; we might want
to revert that eventually.
2019-01-26 01:01:03 +00:00
whitequark
f71e0fffbb
hdl.ast: fix shape calculation for *.
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This was carried over from Migen, and is wrong there too.
Counterexample: 1'sd-1 * 4'sd-4 = 4'sd-4 (but should be 5'sd4).
2019-01-26 00:56:40 +00:00
whitequark
7b25665fde
back.pysim: fix behavior of initial cycle for sync processes.
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The current behavior was introduced in 6570271912e04e4e657027191782b841
2019-01-25 20:37:56 +00:00
whitequark
e33580cf4c
lib.fifo: add AsyncFIFO and AsyncFIFOBuffered.
2019-01-21 16:02:46 +00:00
whitequark
12e04e4ee5
back.pysim: wake up processes before ever committing any values.
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Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
2019-01-21 16:00:25 +00:00
whitequark
b6cff2c098
lib.coding: add GrayEncoder and GrayDecoder.
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Unlike the Migen ones, these are purely combinatorial.
2019-01-20 02:20:34 +00:00
whitequark
9de9272709
lib.fifo: use memory in the FIFO model.
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This is unfortunately more complicated, but results in a much faster
proof.
2019-01-19 09:27:56 +00:00
whitequark
6ea0a12dd4
lib.fifo: use model equivalence to simplify formal specification.
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This is unfortunately slow, and should probably be using theory
of arrays.
2019-01-19 09:27:56 +00:00
whitequark
c5d67b0461
hdl.xfrm: mark internal registers used in lowering Sample().
2019-01-19 07:27:32 +00:00
whitequark
97b990272e
lib.fifo: formally verify FIFO contract.
2019-01-19 00:52:56 +00:00
whitequark
5a831ce31c
lib.fifo: add basic formal specification.
2019-01-17 05:40:25 +00:00
whitequark
fa8e876356
hdl.ast: allow sampling ClockSignal, ResetSignal.
2019-01-17 05:23:06 +00:00
whitequark
8c96675580
hdl.ast: add Past, Stable, Rose, Fell.
2019-01-17 04:31:27 +00:00
whitequark
198efcad31
hdl.xfrm: add SampleLowerer.
2019-01-17 01:41:02 +00:00
whitequark
b3de114d67
hdl.ast: add Sample.
2019-01-17 01:36:27 +00:00
whitequark
b78a2be9f6
lib.fifo: port sync FIFO queues from Migen.
2019-01-16 17:20:38 +00:00
whitequark
cb2f18ee37
hdl.ast: fix naming of Signal.like() signals when tracer fails.
2019-01-16 17:20:38 +00:00
whitequark
b534e92dd5
hdl.ir: allow explicitly requesting flattening.
2019-01-14 17:04:23 +00:00
whitequark
011bf2258e
hdl: make ClockSignal and ResetSignal usable on LHS.
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Fixes #8 .
2019-01-14 15:38:16 +00:00
whitequark
664b4bcb3a
hdl.dsl: cases wider than switch test value are unreachable.
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In 3083c1d6
2019-01-13 08:51:49 +00:00
whitequark
3083c1d6dd
hdl.dsl: accept (but warn on) cases wider than switch test value.
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Fixes #13 .
2019-01-13 08:46:28 +00:00
whitequark
cbf7bd6e31
back.pysim: handle non-driven, non-port signals.
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Fixes #20 .
2019-01-13 08:31:38 +00:00
William D. Jones
2412650f56
hdl.dsl: Support Assert and Assume where an Assign can occur.
2019-01-02 11:17:39 +00:00
whitequark
3c07d8d52c
hdl.rec: include record name in error message.
2019-01-01 03:39:12 +00:00
whitequark
031a9e2616
hdl.rec: use a helpful error on unknown field reference.
2019-01-01 03:35:34 +00:00
whitequark
d78e6c155b
hdl.mem: add DummyPort, for testing and verification.
2019-01-01 03:08:10 +00:00
whitequark
39eb2e8fa7
lib.cdc: fix tests to actually run.
2018-12-29 15:02:44 +00:00
whitequark
849c649259
back.pysim: warn if simulation is not run.
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This would have prevented 3ea35b85
2018-12-29 15:02:04 +00:00
whitequark
92a96e1644
hdl.rec: add basic record support.
2018-12-28 13:22:10 +00:00
whitequark
3ea35b8566
lib.coding: fix tests to actually run, and fix code to fix tests.
2018-12-27 21:45:55 +00:00
whitequark
470d66934f
hdl.dsl: add support for fsm.ongoing().
2018-12-27 16:19:01 +00:00
whitequark
528747703d
lib.coding: port from Migen.
2018-12-26 13:19:34 +00:00
whitequark
fe8cb55204
lib.cdc: add tests for MultiReg.
2018-12-26 12:58:30 +00:00
whitequark
35a44f017f
hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
2018-12-26 12:42:43 +00:00
whitequark
934546e633
hdl.dsl: provide generated values for FSMs.
2018-12-26 12:39:05 +00:00
whitequark
040811c2e5
hdl.ir: add an API for retrieving generated values, like FSM signal.
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This is useful for tests.
2018-12-26 12:35:35 +00:00
whitequark
54e3195dcb
hdl.dsl: implement FSM.
2018-12-26 08:55:04 +00:00
whitequark
98f554aa08
hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
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This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
2018-12-24 02:17:28 +00:00
whitequark
1c7c75a254
hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
2018-12-24 02:02:59 +00:00
whitequark
621dddebfd
hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
2018-12-22 22:19:14 +00:00
