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Author SHA1 Message Date
whitequark 2763b403f1 build.res: simplify emission of port constraints on individual bits. 2019-06-04 08:39:03 +00:00
whitequark 9f643ce005 Clean up imports. 
This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.
 2019-06-04 08:18:50 +00:00
whitequark 3194b5c90b build.run: extract from build.plat. 2019-06-04 07:53:34 +00:00
whitequark c89c2ce941 vendor.board.tinyfpga_bx: clk16 pin does not have a global buffer. 
Fixes #82.
 2019-06-04 06:43:10 +00:00
whitequark 45d1dc1d54 vendor.board.tinyfpga_bx: fix typo. 2019-06-04 06:20:01 +00:00
whitequark 6426b90e4a vendor.conn.pmod: implement. 
Fixes #79.
 2019-06-03 16:49:59 +00:00
whitequark 0fa45b5e14 vendor.board: extract package. 2019-06-03 16:14:59 +00:00
whitequark 2ca0834d41 vendor.tinyfpga_bx: add connectors. 2019-06-03 15:40:57 +00:00
whitequark 7c5461d210 vendor.icestick: add connectors. 2019-06-03 15:15:45 +00:00
whitequark f351e2bd1e vendor.ice40_hx1k_blink_evn: add (some) connectors. 
I have no idea how to lay out the Arduino-like connectors best,
so they're just missing.
 2019-06-03 15:03:49 +00:00
whitequark ed64880cc4 build.{plat,res}: add support for connectors. 
Fixes #77.
 2019-06-03 15:02:15 +00:00
whitequark a013eb1f59 build.dsl: add support for connectors. 2019-06-03 13:47:00 +00:00
whitequark 4c443a7ef5 compat.fhdl.specials: TSTriple is not an elaboratable. 2019-06-03 09:39:38 +00:00
whitequark 639e64c388 vendor.fpga.lattice_ice40: implement differential output buffers. 2019-06-03 09:28:27 +00:00
whitequark 41adcc3f97 vendor.fpga.lattice_ice40: implement differential input buffers. 2019-06-03 08:38:12 +00:00
whitequark 3116d4add2 vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras. 2019-06-03 07:54:28 +00:00
whitequark 185abb492d vendor.fpga.lattice_ice40: implement SDR and DDR I/O buffers. 2019-06-03 07:43:31 +00:00
whitequark b42043f764 lib.io: add i_clk and o_clk to pin layout with xdr>=1. 2019-06-03 07:43:31 +00:00
whitequark a1940c5528 hdl.rec: unbreak hasattr(rec, ...). 
hasattr() requires that AttributeError be raised. Change __getitem__
to raise AttributeError, too, since it is fundamentally just sugar
for getattr().
 2019-06-03 07:43:31 +00:00
whitequark 6fae06aea9 build.{dsl,plat,res}: allow dir="oe". 
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
 2019-06-03 04:42:55 +00:00
whitequark 1eee7cd76f lib.io: allow dir="oe". 
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
 2019-06-03 04:28:53 +00:00
whitequark 9ba2efd86b build.{res,plat}: use xdr=0 as default, not xdr=1. 
The previous behavior was semantically incorrect.
 2019-06-03 03:36:32 +00:00
whitequark cd6488c782 build.res: allow requesting raw ports, with dir="-". 
This provides an escape hatch for the case where the nMigen platform
code is not flexible enough, and a IO buffer primitive needs to be
instantiated directly.
 2019-06-03 03:36:32 +00:00
whitequark c30617fc05 lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer. 2019-06-03 03:36:32 +00:00
whitequark 3327deae92 vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files. 2019-06-03 03:01:56 +00:00
whitequark f417725b10 build.res: if not specified, request resource #0. 
This markedly differs from oMigen system, which would request
consecutive resources. The difference is deliberate; most resources
are singular, so it does not matter for them, and for resources where
it does matter, which pins are requested should not depend on order
of execution of `platform.request`.
 2019-06-03 02:54:17 +00:00
whitequark dc17d06fe9 vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras. 
The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
 2019-06-03 02:51:59 +00:00
whitequark c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports. 
This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
 2019-06-03 02:39:14 +00:00
whitequark b8a61edc2f hdl.dsl: allow adding submodules with computed name, like with domains. 2019-06-03 02:22:55 +00:00
whitequark b64a31255c hdl.ir: accept expanded (kind, name, value) tuples in Instance. 
This is useful for e.g. programmatically generating parameters
without having to mess with kwargs dicts.
 2019-06-03 02:12:01 +00:00
whitequark fb01854372 build.{res,plat}: propagate extras to pin fragment factories. 
This is necessary because on some platforms, like iCE40, extras
become parameters on an IO primitive, since the constraint file
format is not expressive enough for all of them.
 2019-06-03 01:58:43 +00:00
whitequark 268fe6330e build.res: simplify. NFC. 2019-06-03 01:29:20 +00:00
whitequark 98497b2075 build.dsl: require a dict for extras instead of a stringly array. 
Fixes #72.
 2019-06-02 23:36:21 +00:00
whitequark e4ebe03115 vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles. 2019-06-02 04:12:50 +00:00
whitequark 37152c733e vendor.tinyfpga_{b→bx} 2019-06-02 04:11:28 +00:00
whitequark bff08c5016 vendor.tinyfpga_b: fix IO_STANDARD. 2019-06-02 04:04:07 +00:00
Simon Kirkby 358b98e5de vendor.tinyfpga_b: implement. 2019-06-02 01:20:09 +00:00
whitequark 39fad9a955 vendor.icestick: fix typo. 2019-06-02 01:13:03 +00:00
whitequark ba0fcddb2c vendor.ice40_hx1k_blink_evn: implement. 2019-06-01 16:48:07 +00:00
whitequark eab372383a vendor.icestick: implement. 2019-06-01 16:47:20 +00:00
whitequark 321d245e95 vendor.fpga.lattice_ice40: implement. 2019-06-01 16:47:01 +00:00
whitequark b1eab9fb3b build.plat: implement. 2019-06-01 16:43:27 +00:00
whitequark 53ddff9f33 build.res: always return a Pin record. 
In the simple cases, a Pin record consisting of exactly one field
is equivalent in every way to this single field. In the more complex
case however, it can be used as a record, making the code more robust
such that it works with both bidirectional and unidirectional pins.
 2019-06-01 16:41:30 +00:00
whitequark 8c1b5a26b3 build.res: accept a list of clocks in ConstraintManager constructor. 2019-06-01 15:41:41 +00:00
whitequark f17375a60b back.rtlil: allow specifying platform for convert(). 2019-05-26 17:10:56 +00:00
whitequark 578dba263f Add versioneer. 2019-05-26 11:20:13 +00:00
whitequark b0ba960296 hdl.ir: silence unused elaboratable warning on interpreter crash. 2019-05-26 10:48:39 +00:00
Jean-François Nguyen d393c5ec64 build.res: add ConstraintManager. 2019-05-26 01:26:58 +00:00
whitequark 3a9fe31133 build.dsl: make Pins and DiffPairs iterable. 
Returns pin names.
 2019-05-25 22:43:48 +00:00
whitequark 48145cee02 build.dsl: improve repr of Pins() and DiffPairs(). 2019-05-25 22:43:23 +00:00
whitequark 2b7dc37ffe hdl.rec: allow providing fields during construction. 
This allows creating records populated with e.g. signals with custom
names, or sub-records that are instances of Record subclasses.
 2019-05-25 22:06:56 +00:00
whitequark 3392708e2b Consider Instances a part of containing fragment for use-def purposes. 
Fixes #70.
 2019-05-25 20:13:43 +00:00
Chris Osterwood 699fe5a675 Add import so that Tristate.elaborate builds 2019-05-20 16:34:31 +00:00
whitequark c337246fc5 hdl.ir: when adding sync domain to a design, also add it to ports. 
Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
 2019-05-15 06:44:50 +00:00
whitequark 39bc59c924 hdl.ir: during port propagation, defs should take priority over uses. 2019-05-13 15:34:13 +00:00
whitequark 921f506e69 back.rtlil: assign undriven signals to their reset value. 
Fixes #35.
 2019-05-13 08:33:55 +00:00
whitequark 744e33f42d hdl: make all public Value classes other than Record final. 
In some cases, nMigen uses type() instead of isinstance() to dispatch
on types. Make sure all such uses of type() are robust; in addition,
make it clear that nMigen AST classes are not meant to be subclassed.
(Record is an exception.)

Fixes #65.
 2019-05-12 05:40:17 +00:00
whitequark 958cb18b88 hdl.ir: only pull explicitly specified ports to toplevel, if any. 
Fixes #30.
 2019-05-12 05:21:23 +00:00
Jean-François Nguyen 6a77122c2e lib.io: add a name argument to the Pin constructor. 2019-04-24 22:02:20 +00:00
whitequark a982fbe377 build.dsl: style. NFC. 2019-04-24 15:02:30 +00:00
Jean-François Nguyen dd5bd1c88d build: add DSL for defining platform resources. 2019-04-24 11:49:01 +00:00
whitequark 97af266645 back.verilog: allow stripping the src attribute, for cleaner output. 2019-04-22 14:59:53 +00:00
Alain Péteut c8e92c0612 compat.fhdl.specials: fix Tristate, TSTriple. 
* fix TSTriple instance.
* TSTriple, Tristate: tag as Elaboratable
 2019-04-22 09:57:12 +00:00
Alain Péteut 371dc8bebe compat.fhdl.specials: fix Tristate. 2019-04-22 08:49:08 +00:00
whitequark 93d15abcf1 compat.fhdl.specials: fix TSTriple. 2019-04-22 08:15:03 +00:00
whitequark 585514e6ed hdl.ir: rework named port handling for Instances. 
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
 2019-04-22 07:46:47 +00:00
whitequark 44711b7d08 hdl.ir: detect elaboratables that are created but not used. 
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.

Fixes #3.
 2019-04-21 08:52:57 +00:00
whitequark 85ae99c1b4 back.rtlil: emit nmigen.hierarchy attribute. 
Fixes #54.
 2019-04-21 07:55:08 +00:00
whitequark 360bc9b5b4 hdl.ast: improve tests for exceptional conditions. 2019-04-21 07:20:00 +00:00
whitequark 33f9bd2a1d hdl.ast: accept Signals with identical min/max bounds. 
And produce a 0-bit signal.

Fixes #58.
 2019-04-21 07:16:59 +00:00
whitequark 083016d747 back.rtlil: only expand legalized values in Array/Part context on RHS. 
Otherwise the following code fails to compile:

    index = Signal(1)
    array = Array(range(2))
    with m.If(0 == array[index]):
        m.d.sync += index.eq(0)

Fixes #51.
 2019-04-21 06:43:31 +00:00
whitequark ce1eff5464 hdl.rec: implement Record.connect. 
Fixes #31.
 2019-04-21 06:37:08 +00:00
whitequark f22106e5ef back.rtlil: allow record slices on LHS. 2019-04-20 08:12:29 +00:00
whitequark 611c25f909 hdl.rec: fix slicing of records. 2019-04-19 19:55:39 +00:00
whitequark dda8f34d39 hdl.xfrm: handle classes that inherit from Record. 2019-04-18 17:06:33 +00:00
whitequark 287a0531b3 lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
whitequark 50fa2516fa hdl.ast: fix some type checks. 2019-04-10 04:33:44 +00:00
whitequark 0a2a7025a6 hdl.xfrm: allow using FragmentTransformer on any elaboratable. 
Fixes #29.
 2019-04-10 00:23:11 +00:00
whitequark 49eef77c53 hdl: remove deprecated get_fragment() and lower() methods. 2019-04-09 23:53:43 +00:00
whitequark a74cacdc69 hdl.ast: handle a common typo, such as Signal(1, True). 2019-04-03 14:59:01 +00:00
whitequark c9c9307a5e test_sim: add missing add_process(). 
Fixes #43.
 2019-03-28 17:50:14 +00:00
Luke Wren 23a07b955f lib.cdc: add optional reset to MultiReg, and document its use cases. 2019-03-28 05:21:48 +00:00
whitequark a57c72d606 back.rtlil: fix off-by-one in Part legalization. 
Fixes #52.
 2019-03-28 05:12:12 +00:00
anuejn 3c95299c4e hdl.rec: separate record and signal name with __, not _. 
This makes names of signals within records less ambiguous, in case
they themselves have underscores within them.
 2019-03-25 14:26:00 +00:00
whitequark 81ee2db163 hdl.ast: fix typo. 
Fixes #49.
 2019-03-25 10:50:39 +00:00
whitequark 4027317835 lib.fifo: register GrayEncoder output before CDC. 
Without this register, static hazards in the encoder could cause
multiple encoder output bits to toggle, which would be incorrectly
sampled by the 2FF synchronizer.

Reported by @Wren6991.
 2019-03-03 18:23:51 +00:00
whitequark e93bf4bf4b tracer: factor out get_var_name(default=). 2019-03-03 18:21:22 +00:00
whitequark cac4b10b82 hdl.rec: remove __slots__. 
Left in by mistake.
 2019-03-03 18:21:22 +00:00
whitequark 8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. 2019-02-14 20:52:42 +00:00
whitequark 43e4833ddb back.rtlil: accept ast.Const as cell parameter. 2019-01-26 23:25:54 +00:00
whitequark bc5a127fd2 hdl.ast: fix ValueKey for Cat. 2019-01-26 23:25:34 +00:00
whitequark e844b0e095 compat.fhdl.module: fix typo. 2019-01-26 23:08:55 +00:00
whitequark ce7ba70462 compat.fhdl.specials: fix __all__ list. 2019-01-26 22:59:33 +00:00
whitequark 6cd9f7db19 compat.genlib.resetsync: add shim for AsyncResetSynchronizer. 2019-01-26 18:24:36 +00:00
whitequark 2fb85a6170 compat.fifo: fix _FIFOInterface deprecation wrapper. 2019-01-26 18:23:58 +00:00
whitequark f44ca291c1 lib.cdc: add ResetSynchronizer. 2019-01-26 18:07:59 +00:00
whitequark e74dbc3377 back.pysim: support async reset. 2019-01-26 18:07:43 +00:00
whitequark 8686e9aa06 back.pysim: give better names to unnamed fragments and their signals. 
Was: top.#0, top.None_clk
Now: top.U0, top.U0_clk

(U for Unnamed, or similarly, an unit refdes.)
 2019-01-26 18:07:16 +00:00
whitequark b133eb735f back.rtlil: accept any elaboratable, not just fragments. 2019-01-26 16:11:29 +00:00
whitequark 4bf80a6e33 compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00