whitequark
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b58715c5dc
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ast, back.pysim: allow specifying user-defined decoders for signals.
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2018-12-14 09:02:29 +00:00 |
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whitequark
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bb843cb40c
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back.pysim: fix completely broken codegen for Switch.
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2018-12-14 08:51:36 +00:00 |
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whitequark
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6aefd0c04c
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back.pysim: raise an exception if delta cycles blow a process deadline.
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2018-12-14 08:10:21 +00:00 |
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whitequark
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a10791e160
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back.pysim: if requested, write a gtkw file with a useful preset.
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2018-12-14 08:04:29 +00:00 |
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whitequark
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cb998d891b
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back.pysim: explain how delta cycles work.
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2018-12-14 07:26:26 +00:00 |
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whitequark
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e4d08d2855
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back.pysim: delay clock processes by one half period.
Makes it easier to see initial delta cycles.
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2018-12-14 05:17:43 +00:00 |
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whitequark
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3bb7a87e0f
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back.pysim: implement "sync processes", like migen.sim generators.
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2018-12-14 05:13:58 +00:00 |
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whitequark
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d791b77cc8
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back.pysim: allow suspending processes until a tick in a domain.
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2018-12-14 04:33:06 +00:00 |
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whitequark
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3e59d857e1
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back.pysim: use bare ints for signal values (-5% runtime).
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2018-12-14 03:05:57 +00:00 |
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whitequark
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b09f4b10ee
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back.pysim: collect handlers before running (-5% runtime).
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2018-12-13 18:34:44 +00:00 |
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whitequark
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a7ebc02bdd
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back.pysim: allow multiple registered handlers per signal.
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2018-12-13 18:28:11 +00:00 |
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whitequark
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6a4004ef8d
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back.pysim: fix handling of process termination.
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2018-12-13 18:17:58 +00:00 |
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whitequark
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fb27c2520b
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back.pysim: new simulator backend (WIP).
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2018-12-13 18:02:46 +00:00 |
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whitequark
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07c818e077
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fhdl.ir: move Fragment prepare logic from back.rtlil.
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2018-12-13 14:34:07 +00:00 |
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whitequark
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ac498414ab
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back.verilog: remove debug code.
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2018-12-13 13:42:54 +00:00 |
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whitequark
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90f1503c91
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fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
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2018-12-13 13:12:31 +00:00 |
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whitequark
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6251c95d4e
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compat.genlib.fsm: import/wrap Migen code.
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2018-12-13 12:41:19 +00:00 |
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whitequark
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bb04c9e0da
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fhdl, back: trace and emit source locations of values.
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2018-12-13 11:44:06 +00:00 |
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whitequark
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859c2dbcf0
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back.rtlil: never give subfragment cells names starting with $.
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2018-12-13 11:30:16 +00:00 |
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whitequark
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72257b6935
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fhdl.ir: implement clock domain propagation.
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2018-12-13 11:01:03 +00:00 |
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whitequark
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fde2471963
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fhdl.ir: remove iter_domains().
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2018-12-13 10:18:57 +00:00 |
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whitequark
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f4340c19bb
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fhdl: cd_name→domain.
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2018-12-13 10:15:01 +00:00 |
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whitequark
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d2e2d00e45
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fhdl.cd: rename ClockDomain.{reset→rst}.
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2018-12-13 07:27:27 +00:00 |
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whitequark
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4e32f6b8de
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back.verilog: detect undriven public wires using Yosys.
This should never happen, and is certainly a logic bug in nMigen.
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2018-12-13 04:59:48 +00:00 |
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whitequark
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27d3dfc453
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back.rtlil: fix swapped operands in sync assign.
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2018-12-13 04:34:22 +00:00 |
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whitequark
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6c7f98e964
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back.rtlil: explain logic for CD reset insertion.
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2018-12-13 03:51:00 +00:00 |
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whitequark
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2c67a620ee
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back.rtlil: explicitly set the top module.
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2018-12-13 03:50:04 +00:00 |
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whitequark
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4df5c5de65
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fhdl.ir: explain how port enumeration works.
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2018-12-13 03:31:13 +00:00 |
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whitequark
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f86ec1e7ef
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back.rtlil: explain how RTLIL conversion works.
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2018-12-13 03:22:01 +00:00 |
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whitequark
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a17a9e355d
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back.rtlil: give clocks and resets nicer names.
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2018-12-13 02:43:02 +00:00 |
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whitequark
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b42620e490
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back.rtlil: match shape of $mux ports A/B/Y.
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2018-12-13 02:35:46 +00:00 |
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whitequark
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f0f4c0ce61
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fhdl.ast: bits_sign→shape.
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2018-12-13 02:06:58 +00:00 |
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whitequark
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0fac1f8d0f
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fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
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2018-12-12 12:38:24 +00:00 |
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whitequark
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aab01d9e59
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fhdl.ast.Signal: implement attrs field.
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2018-12-12 11:30:40 +00:00 |
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whitequark
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851ed06769
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ClockDomain.{rst→reset}, for consistency with ResetInserter.
nmigen.compat.ClockDomain would alias this, for Migen compatibility.
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2018-12-12 09:49:02 +00:00 |
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whitequark
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4d3258013d
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Initial commit.
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2018-12-12 03:18:44 +00:00 |
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