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Author SHA1 Message Date
whitequark c4276f7cf7 lib.io: pass pin to platform.get_tristate(). 2019-01-14 21:39:19 +00:00
whitequark b534e92dd5 hdl.ir: allow explicitly requesting flattening. 2019-01-14 17:04:23 +00:00
whitequark 6f66885c09 lib.io: lower to platform-independent tristate buffer. 2019-01-14 16:50:04 +00:00
whitequark 011bf2258e hdl: make ClockSignal and ResetSignal usable on LHS. 
Fixes #8.
 2019-01-14 15:38:16 +00:00
whitequark 664b4bcb3a hdl.dsl: cases wider than switch test value are unreachable. 
In 3083c1d6 they were erroneously fixed via truncation.
 2019-01-13 08:51:49 +00:00
whitequark 3083c1d6dd hdl.dsl: accept (but warn on) cases wider than switch test value. 
Fixes #13.
 2019-01-13 08:46:28 +00:00
whitequark cbf7bd6e31 back.pysim: handle non-driven, non-port signals. 
Fixes #20.
 2019-01-13 08:31:38 +00:00
whitequark 06faeee357 back.verilog: better error message if Yosys is not found. 
Fixes #17.
 2019-01-13 08:10:23 +00:00
whitequark 307de722cb back.verilog: remove undriven check. 
This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.

Fixes #23.
 2019-01-08 22:43:09 +00:00
Adam Greig 560bb007cc Give the top level scope a name to fix VCD hierarchy. 2019-01-06 00:10:37 +00:00
whitequark a2b04d71d0 hdl.ast: allow slicing [n:n] into n-bit value. 2019-01-02 18:14:57 +00:00
whitequark ef1e0b8d55 back.rtlil: translate empty slices correctly. 2019-01-02 18:14:29 +00:00
William D. Jones f31055a4ef back.rtlil: Generate RTLIL for Assert/Assume statements. 2019-01-02 11:17:39 +00:00
William D. Jones f77dc40256 hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children. 2019-01-02 11:17:39 +00:00
William D. Jones 2412650f56 hdl.dsl: Support Assert and Assume where an Assign can occur. 2019-01-02 11:17:39 +00:00
William D. Jones e6517a33c7 hdl.ast: Add Assert and Assign statements. 2019-01-02 11:17:39 +00:00
whitequark ea7e19ed5c hdl.ast: experimentally add Value._as_const. 
Useful for writing e.g. decoders that accept Cat, etc as argument.
 2019-01-01 09:50:39 +00:00
whitequark 1a9dcd2f28 back.rtlil: fix typo. 2019-01-01 08:50:28 +00:00
whitequark 3c07d8d52c hdl.rec: include record name in error message. 2019-01-01 03:39:12 +00:00
whitequark 031a9e2616 hdl.rec: use a helpful error on unknown field reference. 2019-01-01 03:35:34 +00:00
whitequark d78e6c155b hdl.mem: add DummyPort, for testing and verification. 2019-01-01 03:08:10 +00:00
whitequark ae3c5834ed back.rtlil: match shape of Array elements to ArrayProxy shape. 
Fixes #15.
 2018-12-31 03:43:34 +00:00
whitequark cdc40eaa9b back.rtlil: fix typo. 2018-12-31 03:37:38 +00:00
whitequark 39eb2e8fa7 lib.cdc: fix tests to actually run. 2018-12-29 15:02:44 +00:00
whitequark 849c649259 back.pysim: warn if simulation is not run. 
This would have prevented 3ea35b85.
 2018-12-29 15:02:04 +00:00
whitequark 92a96e1644 hdl.rec: add basic record support. 2018-12-28 13:22:10 +00:00
whitequark d66bbb0df8 tracer: factor out get_src_loc(). 2018-12-28 01:31:24 +00:00
whitequark 3ea35b8566 lib.coding: fix tests to actually run, and fix code to fix tests. 2018-12-27 21:45:55 +00:00
whitequark 470d66934f hdl.dsl: add support for fsm.ongoing(). 2018-12-27 16:19:01 +00:00
whitequark de50ccec90 hdl.mem: add missing __all__. 2018-12-27 16:19:01 +00:00
Jean-François Nguyen 73ed870309 compat.genlib.coding: fix import. 2018-12-26 14:30:01 +00:00
whitequark 528747703d lib.coding: port from Migen. 2018-12-26 13:19:34 +00:00
whitequark fe8cb55204 lib.cdc: add tests for MultiReg. 2018-12-26 12:58:30 +00:00
whitequark 35a44f017f hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too. 2018-12-26 12:42:43 +00:00
whitequark 934546e633 hdl.dsl: provide generated values for FSMs. 2018-12-26 12:39:05 +00:00
whitequark 040811c2e5 hdl.ir: add an API for retrieving generated values, like FSM signal. 
This is useful for tests.
 2018-12-26 12:35:35 +00:00
whitequark 597d778cf6 examples: add an FSM usage example (UART receiver). 2018-12-26 10:10:27 +00:00
whitequark 72039b6072 hdl.dsl: add signal decoder to FSM state signal. 2018-12-26 09:45:12 +00:00
whitequark 54e3195dcb hdl.dsl: implement FSM. 2018-12-26 08:55:04 +00:00
whitequark b4fbef65ca back.rtlil: clarify $verilog_initial_trigger behavior. NFC. 2018-12-26 06:45:57 +00:00
whitequark 010ddb96b5 back.rtlil: unbreak d47c1f8a. 2018-12-24 19:11:07 +00:00
whitequark f05bd2a137 hdl.mem: allow omitting memory simulation logic. 
Trying to transform very large arrays is slow.
 2018-12-24 11:53:59 +00:00
whitequark d47c1f8a8a back.rtlil: use one $meminit cell, not one per word. 
This is *far* more efficient.
 2018-12-24 11:53:58 +00:00
whitequark 98f554aa08 hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. 
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
 2018-12-24 02:17:28 +00:00
whitequark 1c7c75a254 hdl.xfrm: implement SwitchCleaner, for pruning empty switches. 2018-12-24 02:02:59 +00:00
whitequark fc0fb9d89f back.rtlil: always output negative values as two's complement. 
- is valid in RTLIL but means something entirely different.
 2018-12-24 01:38:32 +00:00
whitequark 5702767263 back.rtlil: emit dummy logic to work around Verilog deficiencies. 2018-12-23 10:14:42 +00:00
whitequark 9faa1d3742 back.rtlil: do not translate empty fragments. 
The resulting Verilog confuses some frontends.
 2018-12-23 09:20:02 +00:00
whitequark 45a474788c back.rtlil: only translate switch tests once. 
This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
 2018-12-23 07:17:52 +00:00
whitequark 4e49772f67 cli: generate: guess file type from extension. 2018-12-23 07:13:17 +00:00