Commit graph

276 commits

Author SHA1 Message Date
whitequark
e9c75f7ca1 hdl.ast: improve repr() for Shape.
The default __repr__() from typing.NamedTuple does not include
the module name, so the replacement (which uses the preferred syntax
for specifying these shapes) doesn't either.
2020-04-12 03:59:56 +00:00
Jacob Lifshay
995f3a147b Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation
Fixes #344
2020-04-02 02:46:44 +00:00
whitequark
2d1e12d00c hdl.ast: implement abs() on values. 2020-03-22 20:50:10 +00:00
Stuart Olsen
7b9c8b440f
back.pysim: implement modulus operator. 2020-03-15 05:22:03 +00:00
awygle
4601dd0a69
Correctly handle resets in AsyncFIFO.
This commit improves handling of resets in AsyncFIFO in two ways:
  * First, resets no longer violate Gray counter CDC invariants.
  * Second, write domain reset now empties the entire FIFO.
2020-03-14 23:26:07 +00:00
awygle
2f8669cad6
lib.cdc: extract AsyncFFSynchronizer.
In some cases, it is necessary to synchronize a reset-like signal but
a new clock domain is not desirable. To address these cases, extract
the implementation of ResetSynchronizer into AsyncFFSynchronizer,
and replace ResetSynchronizer with a thin wrapper around it.
2020-03-08 21:37:40 +00:00
whitequark
ec7aee62ea back.pysim: fix RHS codegen for Cat() and Repl(..., 0).
Fixes #325.
2020-02-19 01:21:00 +00:00
awygle
fcbabfeefc
nmigen.lib.cdc: port PulseSynchronizer.
Co-authored-by: Luke Wren <wren6991@gmail.com>
2020-02-16 06:51:53 +00:00
whitequark
3b6727152e test_build_res: fix after commit 3e2ecdf2. 2020-02-07 00:07:19 +00:00
whitequark
27b47faf16 hdl.ast: add Value.{as_signed,as_unsigned}.
Before this commit, there was no way to do so besides creating and
assigning an intermediate signal, which could not be extracted into
a helper function due to Module statefulness.

Fixes #292.
2020-02-06 18:27:55 +00:00
whitequark
9301e31b69 test_lib_fifo: define all referenced FSM states.
Broken in commit a1c58633.
2020-02-06 18:10:15 +00:00
whitequark
a1c58633e6 hdl.dsl: make referencing undefined FSM states an error.
Before this commit, doing something like:

    with m.FSM():
        with m.State("FOO"):
            m.next = "bAR"
        with m.State("BAR"):
            m.next = "FOO"

would silently create an empty state `bAR` and get stuck in it until
the module is reset. This was done intentionally (in Migen, this code
would in fact miscompile), but in retrospect was clearly a bad idea;
it turns typos into bugs, while in the rare case that branching to
a completely empty state is desired, it is trivial to define one.

Fixes #315.
2020-02-06 17:47:46 +00:00
whitequark
97cc78a3db hdl.ir: type check ports.
Fixes #290.
2020-02-06 17:33:41 +00:00
whitequark
3df429703c hdl.dsl: reject name mismatch in m.domains.<name> +=.
This would violate invariants later in the elaboration process.

Fixes #282.
2020-02-06 16:13:59 +00:00
whitequark
86b57fe6b6 hdl.dsl: type check when adding to m.domains. 2020-02-06 15:19:16 +00:00
whitequark
31cd72c0b6 hdl.mem: add synthesis attribute support.
Fixes #291.
2020-02-06 14:53:16 +00:00
whitequark
dfcf7938ea hdl.{ast,dsl}: allow whitespace in bit patterns.
Fixes #316.
2020-02-04 07:54:54 +00:00
whitequark
49758a3a0c hdl.ast: prohibit shifts by signed value.
These are not desirable in a HDL, and currently elaborate to broken
RTLIL (after YosysHQ/yosys#1551); prohibit them completely, like
we already do for division and modulo.

Fixes #302.
2020-02-01 23:04:25 +00:00
whitequark
6fd7cbad0d hdl.dsl: don't allow inheriting from Module.
`Module` is an object with a lot of complex and sometimes fragile
behavior that overrides Python attribute accessors and so on.
To prevent user designs from breaking when it is changed, it is not
supposed to be inherited from (unlike in Migen), but rather returned
from the elaborate() method. This commit makes sure it will not be
inherited from by accident (most likely by users familiar with
Migen).

Fixes #286.
2020-02-01 02:15:45 +00:00
whitequark
687d3a3df7 hdl.dsl: add missing case width check for Enum values.
Fixes #305.
2020-01-31 23:14:16 +00:00
whitequark
9964fc6b57 hdl.dsl: make if m.{If,Elif,Else}(...) a syntax error.
A common typo, and hard to notice when it's silently ignored.

Fixes #284.
2020-01-31 06:37:45 +00:00
Jaro Habiger
ec3a21939e build.dsl: allow strings to be used as connector numbers.
Fixes #311.
2020-01-31 03:11:34 +00:00
whitequark
a7be3b480a hdl.ir: resolve hierarchy conflicts before creating missing domains.
Otherwise, code such as:

    m.submodules.a = (something with cd_sync)
    m.submodules.b = (something with cd_sync)
    m.d.b_sync += x.eq(y)

causes an assertion failure.

Fixes #304 (again).
2020-01-18 10:30:36 +00:00
whitequark
7cb3095334 hdl.xfrm: transform drivers as well in DomainRenamer.
This is necessary because drivers may be late bound.

Fixes #304.
2020-01-17 02:13:46 +00:00
whitequark
e18385b613 Remove everything deprecated in nmigen 0.1.
Closes #275.
2020-01-12 13:59:26 +00:00
Staf Verhaegen
e4e26717be Signal: allow to use integral Enum for reset value. 2020-01-11 09:03:20 +00:00
Marcin Kościelnicki
67650214b7 hdl.ast: Fix width for unary minus operator on signed argument.
To properly represent a negation of a signed X-bit quantity we may, in
general, need a signed (X+1)-bit signal — for example, negation of
3-bit -4 is 4, which is not representable in signed 3 bits.
2019-12-04 06:55:35 +00:00
whitequark
7df70059d1 back.pysim: redesign the simulator.
The redesign introduces no fundamental incompatibilities, but it does
involve minor breaking changes:
  * The simulator commands were moved from hdl.ast to back.pysim
    (instead of only being reexported from back.pysim).
  * back.pysim.DeadlineError was removed.

Summary of changes:
  * The new simulator compiles HDL to Python code and is >6x faster.
    (The old one compiled HDL to lots of Python lambdas.)
  * The new simulator is a straightforward, rigorous implementation
    of the Synchronous Reactive Programming paradigm, instead of
    a pile of ad-hoc code with no particular design driving it.
  * The new simulator never raises DeadlineError, and there is no
    limit on the amount of delta cycles.
  * The new simulator robustly handles multiclock designs.
  * The new simulator can be reset, such that the compiled design
    can be reused, which can save significant runtime with large
    designs.
  * Generators can no longer be added as processes, since that would
    break reset(); only generator functions may be. If necessary,
    they may be added by wrapping them into a generator function;
    a deprecated fallback does just that. This workaround will raise
    an exception if the simulator is reset and restarted.
  * The new simulator does not depend on Python extensions.
    (The old one required bitarray, which did not provide wheels.)

Fixes #28.
Fixes #34.
Fixes #160.
Fixes #161.
Fixes #215.
Fixes #242.
Fixes #262.
2019-11-28 21:05:34 +00:00
whitequark
56bb42aff2 hdl.ir: for instance ports, prioritize defs over uses.
Fixes #274.
2019-11-26 21:19:03 +00:00
whitequark
834fe3c700 build.plat: in Platform.add_file(), allow adding exact duplicates. 2019-11-15 23:40:44 +00:00
whitequark
fe400b5dbc test: add tests for build.plat.Platform.add_file. 2019-11-15 23:39:13 +00:00
whitequark
9749c70730 hdl.ir: lower domains before resolving hierarchy conflicts.
Otherwise, two subfragments with the same local clock domain would
not be able to drive its clock or reset signals. This can be easily
hit if using two ResetSynchronizers in one module.

Fixes #265.
2019-11-07 08:20:27 +00:00
whitequark
75d0fcd639 test: use #nmigen: magic comment instead of monkey patch.
Also, fix missing and incorrect src_loc_at arguments where
appropriate so the testsuite passes without warnings.
2019-10-26 06:37:08 +00:00
whitequark
51269ad4a0 hdl.ast: simplify {bit,word}_select with constant offset.
We don't have any other convenient shortcut for x[off*w:(off+1)*w],
but using word_select to extract a single static range would result
in severe bloat of emitted code through expansion to dead branches.
Recognize and simplify this pattern.
2019-10-26 00:09:53 +00:00
whitequark
2f9dab361f {,_}tools→{,_}utils
In context of nMigen, "tools" means "parts of toolchain", so it is
confusing to have a completely unrelated module also called "tools".
2019-10-13 18:53:38 +00:00
whitequark
29253295ee hdl.ir: allow ClockSignal and ResetSignal in ports.
Fixes #248.
2019-10-13 03:39:56 +00:00
whitequark
722b3879f4 hdl.ir: cast instance port connections to Values.
Fixes #249.
2019-10-13 03:19:17 +00:00
whitequark
a7e3b80409 hdl.ast: rename Slice.end back to Slice.stop.
It used to be called .stop in oMigen, and it's also called .stop in
Python range and slice objects, so keep that.
2019-10-12 22:40:48 +00:00
whitequark
da48c05bdf _tools: extract most utility methods to a private package.
We don't want to guarantee backwards compatibility for most of them.
2019-10-12 22:40:48 +00:00
whitequark
b90687c988 Rename remaining wrap methods to cast.
Following commit d72d4a55.
2019-10-11 13:28:26 +00:00
whitequark
a658cb2bbf hdl.ast: deprecate shapes like (1, True) in favor of signed(1).
This is a great improvement in clarity.
2019-10-11 13:22:08 +00:00
whitequark
706bfaf5e1 hdl.ast: deprecate Signal.{range,enum}.
Although constructor methods can improve clarity, there are many
contexts in which it is useful to use range() as a shape: notably
Layout, but also Const and AnyConst/AnyValue. Instead of duplicating
these constructor methods everywhere (which is not even easily
possible for Layout), use casting to Shape, introduced in 6aabdc0a.

Fixes #225.
2019-10-11 13:07:42 +00:00
whitequark
6aabdc0a73 hdl.ast: add an explicit Shape class, included in prelude.
Shapes have long been a part of nMigen, but represented using tuples.
This commit adds a Shape class (using namedtuple for backwards
compatibility), and accepts anything castable to Shape (including
enums, ranges, etc) anywhere a tuple was accepted previously.

In addition, `signed(n)` and `unsigned(n)` are added as aliases for
`Shape(n, signed=True)` and `Shape(n, signed=False)`, transforming
code such as `Signal((8, True))` to `Signal(signed(8))`.
These aliases are also included in prelude.

Preparation for #225.
2019-10-11 12:52:41 +00:00
whitequark
db960e7c30 Consistently use {!r}, not '{!r}' in diagnostics.
This can cause confusion:
  * If the erroneous object is None, it is printed as 'None', which
    appears as a string (and could be the result of converting None
    to a string.)
  * If the erroneous object is a string, it is printed as ''<val>'',
    which is a rather strange combination of quotes.
2019-10-11 11:47:42 +00:00
whitequark
7ff4c6ce43 hdl.ast: simplify enum handling. 2019-10-11 11:16:00 +00:00
whitequark
d72d4a55fd hdl.ast: Value.{wrap→cast}
Preparation for #225.
2019-10-11 10:49:34 +00:00
whitequark
de34728bf8 hdl.ast: prohibit signed divisors.
See #238.
2019-10-04 07:49:24 +00:00
whitequark
751ae33fe1 build.dsl: accept Pins(invert=True).
The PinsN() form is still preferred, but Pins(invert=) form is useful
for code generic over pin polarity.
2019-10-03 02:44:43 +00:00
whitequark
9458de2079 hdl.ast: don't crash on Mux(<bool>, ...).
Fixes #240.
2019-10-02 08:30:15 +00:00
whitequark
1621ceb65a hdl.ast: actually implement the // operator. 2019-09-28 19:33:24 +00:00