Commit graph

390 commits

Author SHA1 Message Date
whitequark
1d3e9c8331 build.plat: allow (easily) overriding with an empty string on Windows. 2019-06-04 11:33:51 +00:00
whitequark
39ca0e6fa6 compat.fhdl.module: CompatModule should be elaboratable.
Fixes #83.
2019-06-04 11:11:31 +00:00
whitequark
4310254103 build.res: use ConstraintError iff a constraint invariant is violated.
In particular don't use it for type errors.
2019-06-04 11:00:11 +00:00
whitequark
51c03ca391 hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}. 2019-06-04 10:26:01 +00:00
whitequark
1b54eb80da vendor.board: split off into nmigen-boards package.
The iCE40 programmers are also moved, since they're board-specific.
(It looks like iceprog isn't, but it only works with Lattice
evaluation kits.)

Fixes #80.
2019-06-04 09:52:33 +00:00
whitequark
316ba10207 build.run: simplify using build products locally, e.g. for programming. 2019-06-04 09:13:24 +00:00
whitequark
2763b403f1 build.res: simplify emission of port constraints on individual bits. 2019-06-04 08:39:03 +00:00
whitequark
9f643ce005 Clean up imports.
This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.
2019-06-04 08:18:50 +00:00
whitequark
3194b5c90b build.run: extract from build.plat. 2019-06-04 07:53:34 +00:00
whitequark
c89c2ce941 vendor.board.tinyfpga_bx: clk16 pin does not have a global buffer.
Fixes #82.
2019-06-04 06:43:10 +00:00
whitequark
45d1dc1d54 vendor.board.tinyfpga_bx: fix typo. 2019-06-04 06:20:01 +00:00
whitequark
6426b90e4a vendor.conn.pmod: implement.
Fixes #79.
2019-06-03 16:49:59 +00:00
whitequark
0fa45b5e14 vendor.board: extract package. 2019-06-03 16:14:59 +00:00
whitequark
2ca0834d41 vendor.tinyfpga_bx: add connectors. 2019-06-03 15:40:57 +00:00
whitequark
7c5461d210 vendor.icestick: add connectors. 2019-06-03 15:15:45 +00:00
whitequark
f351e2bd1e vendor.ice40_hx1k_blink_evn: add (some) connectors.
I have no idea how to lay out the Arduino-like connectors best,
so they're just missing.
2019-06-03 15:03:49 +00:00
whitequark
ed64880cc4 build.{plat,res}: add support for connectors.
Fixes #77.
2019-06-03 15:02:15 +00:00
whitequark
a013eb1f59 build.dsl: add support for connectors. 2019-06-03 13:47:00 +00:00
whitequark
4c443a7ef5 compat.fhdl.specials: TSTriple is not an elaboratable. 2019-06-03 09:39:38 +00:00
whitequark
639e64c388 vendor.fpga.lattice_ice40: implement differential output buffers. 2019-06-03 09:28:27 +00:00
whitequark
41adcc3f97 vendor.fpga.lattice_ice40: implement differential input buffers. 2019-06-03 08:38:12 +00:00
whitequark
3116d4add2 vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras. 2019-06-03 07:54:28 +00:00
whitequark
185abb492d vendor.fpga.lattice_ice40: implement SDR and DDR I/O buffers. 2019-06-03 07:43:31 +00:00
whitequark
b42043f764 lib.io: add i_clk and o_clk to pin layout with xdr>=1. 2019-06-03 07:43:31 +00:00
whitequark
a1940c5528 hdl.rec: unbreak hasattr(rec, ...).
hasattr() requires that AttributeError be raised. Change __getitem__
to raise AttributeError, too, since it is fundamentally just sugar
for getattr().
2019-06-03 07:43:31 +00:00
whitequark
6fae06aea9 build.{dsl,plat,res}: allow dir="oe".
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
2019-06-03 04:42:55 +00:00
whitequark
1eee7cd76f lib.io: allow dir="oe".
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
2019-06-03 04:28:53 +00:00
whitequark
9ba2efd86b build.{res,plat}: use xdr=0 as default, not xdr=1.
The previous behavior was semantically incorrect.
2019-06-03 03:36:32 +00:00
whitequark
cd6488c782 build.res: allow requesting raw ports, with dir="-".
This provides an escape hatch for the case where the nMigen platform
code is not flexible enough, and a IO buffer primitive needs to be
instantiated directly.
2019-06-03 03:36:32 +00:00
whitequark
c30617fc05 lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer. 2019-06-03 03:36:32 +00:00
whitequark
3327deae92 vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files. 2019-06-03 03:01:56 +00:00
whitequark
f417725b10 build.res: if not specified, request resource #0.
This markedly differs from oMigen system, which would request
consecutive resources. The difference is deliberate; most resources
are singular, so it does not matter for them, and for resources where
it does matter, which pins are requested should not depend on order
of execution of `platform.request`.
2019-06-03 02:54:17 +00:00
whitequark
dc17d06fe9 vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.
The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
2019-06-03 02:51:59 +00:00
whitequark
c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports.
This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
2019-06-03 02:39:14 +00:00
whitequark
b8a61edc2f hdl.dsl: allow adding submodules with computed name, like with domains. 2019-06-03 02:22:55 +00:00
whitequark
b64a31255c hdl.ir: accept expanded (kind, name, value) tuples in Instance.
This is useful for e.g. programmatically generating parameters
without having to mess with kwargs dicts.
2019-06-03 02:12:01 +00:00
whitequark
fb01854372 build.{res,plat}: propagate extras to pin fragment factories.
This is necessary because on some platforms, like iCE40, extras
become parameters on an IO primitive, since the constraint file
format is not expressive enough for all of them.
2019-06-03 01:58:43 +00:00
whitequark
268fe6330e build.res: simplify. NFC. 2019-06-03 01:29:20 +00:00
whitequark
98497b2075 build.dsl: require a dict for extras instead of a stringly array.
Fixes #72.
2019-06-02 23:36:21 +00:00
whitequark
e4ebe03115 vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles. 2019-06-02 04:12:50 +00:00
whitequark
37152c733e vendor.tinyfpga_{b→bx} 2019-06-02 04:11:28 +00:00
whitequark
bff08c5016 vendor.tinyfpga_b: fix IO_STANDARD. 2019-06-02 04:04:07 +00:00
Simon Kirkby
358b98e5de vendor.tinyfpga_b: implement. 2019-06-02 01:20:09 +00:00
whitequark
39fad9a955 vendor.icestick: fix typo. 2019-06-02 01:13:03 +00:00
whitequark
ba0fcddb2c vendor.ice40_hx1k_blink_evn: implement. 2019-06-01 16:48:07 +00:00
whitequark
eab372383a vendor.icestick: implement. 2019-06-01 16:47:20 +00:00
whitequark
321d245e95 vendor.fpga.lattice_ice40: implement. 2019-06-01 16:47:01 +00:00
whitequark
b1eab9fb3b build.plat: implement. 2019-06-01 16:43:27 +00:00
whitequark
53ddff9f33 build.res: always return a Pin record.
In the simple cases, a Pin record consisting of exactly one field
is equivalent in every way to this single field. In the more complex
case however, it can be used as a record, making the code more robust
such that it works with both bidirectional and unidirectional pins.
2019-06-01 16:41:30 +00:00
whitequark
8c1b5a26b3 build.res: accept a list of clocks in ConstraintManager constructor. 2019-06-01 15:41:41 +00:00