whitequark
ef1e0b8d55
back.rtlil: translate empty slices correctly.
2019-01-02 18:14:29 +00:00
William D. Jones
f31055a4ef
back.rtlil: Generate RTLIL for Assert/Assume statements.
2019-01-02 11:17:39 +00:00
William D. Jones
f77dc40256
hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children.
2019-01-02 11:17:39 +00:00
whitequark
1a9dcd2f28
back.rtlil: fix typo.
2019-01-01 08:50:28 +00:00
whitequark
ae3c5834ed
back.rtlil: match shape of Array elements to ArrayProxy shape.
...
Fixes #15 .
2018-12-31 03:43:34 +00:00
whitequark
cdc40eaa9b
back.rtlil: fix typo.
2018-12-31 03:37:38 +00:00
whitequark
849c649259
back.pysim: warn if simulation is not run.
...
This would have prevented 3ea35b85
2018-12-29 15:02:04 +00:00
whitequark
92a96e1644
hdl.rec: add basic record support.
2018-12-28 13:22:10 +00:00
whitequark
fe8cb55204
lib.cdc: add tests for MultiReg.
2018-12-26 12:58:30 +00:00
whitequark
b4fbef65ca
back.rtlil: clarify $verilog_initial_trigger behavior. NFC.
2018-12-26 06:45:57 +00:00
whitequark
010ddb96b5
back.rtlil: unbreak d47c1f8a.
2018-12-24 19:11:07 +00:00
whitequark
d47c1f8a8a
back.rtlil: use one $meminit cell, not one per word.
...
This is *far* more efficient.
2018-12-24 11:53:58 +00:00
whitequark
98f554aa08
hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
...
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
2018-12-24 02:17:28 +00:00
whitequark
1c7c75a254
hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
2018-12-24 02:02:59 +00:00
whitequark
fc0fb9d89f
back.rtlil: always output negative values as two's complement.
...
- is valid in RTLIL but means something entirely different.
2018-12-24 01:38:32 +00:00
whitequark
5702767263
back.rtlil: emit dummy logic to work around Verilog deficiencies.
2018-12-23 10:14:42 +00:00
whitequark
9faa1d3742
back.rtlil: do not translate empty fragments.
...
The resulting Verilog confuses some frontends.
2018-12-23 09:20:02 +00:00
whitequark
45a474788c
back.rtlil: only translate switch tests once.
...
This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
2018-12-23 07:17:52 +00:00
whitequark
2b6ddbb713
back.rtlil: fix swapped operands in mux codegen.
2018-12-23 06:47:38 +00:00
whitequark
59c7540aeb
back.rtlil: split processes as finely as possible.
...
This makes simulation work correctly (by introducing delta cycles,
and therefore, making the overall Verilog simulation deterministic)
at the price of pessimizing mux trees generated by Yosys and Synplify
frontends, sometimes severely.
2018-12-22 10:03:16 +00:00
whitequark
d29929912f
back.rtlil: remove useless condition. NFC.
2018-12-22 07:24:15 +00:00
whitequark
98a9744be4
hdl.xfrm: Abstract*Transformer→*Visitor
2018-12-22 06:03:39 +00:00
whitequark
37b81309d3
back.rtlil: always initialize the entire memory.
...
This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.
2018-12-22 05:27:42 +00:00
whitequark
6ee80408bb
back.verilog: do not rename internal signals.
...
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
2018-12-22 00:53:40 +00:00
whitequark
48d13e47ec
back.pysim: handle out of bounds ArrayProxy indexes.
2018-12-21 12:32:08 +00:00
whitequark
7ae7683fed
back.pysim: give numeric names to unnamed subfragments in VCD.
2018-12-21 12:29:33 +00:00
whitequark
a40e2cac4b
back.pysim: fix an issue with too few funclet slots.
2018-12-21 10:25:28 +00:00
whitequark
a061bfaa6c
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
2018-12-21 04:22:16 +00:00
whitequark
8d58cbf230
back.rtlil: more consistent prefixing for subfragment port wires.
2018-12-21 04:21:11 +00:00
whitequark
2b4a8510ca
back.rtlil: implement memories.
2018-12-21 01:55:59 +00:00
whitequark
6672ab2e3f
back.rtlil: explicitly pad constants with zeroes.
...
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
2018-12-21 01:51:18 +00:00
whitequark
221f108fbe
back.rtlil: fix translation of Cat.
2018-12-21 01:48:02 +00:00
whitequark
f7fec804ec
ir: allow non-Signals in Instance ports.
2018-12-20 23:40:40 +00:00
whitequark
dbbcc49a71
hdl.ast: Cat.{operands→parts}
2018-12-18 19:15:50 +00:00
whitequark
4199674edd
back.pysim: implement *.
2018-12-18 18:02:21 +00:00
whitequark
07e9cfa939
test.sim: add tests for sync functionality and errors.
2018-12-18 17:53:50 +00:00
whitequark
7fa82a70be
back.pysim: eliminate most dictionary lookups.
...
This makes the Glasgow testsuite about 30% faster.
2018-12-18 16:36:54 +00:00
whitequark
c5f169988b
back.pysim: use arrays instead of dicts for signal values.
...
This makes the Glasgow testsuite about 40% faster.
2018-12-18 05:20:20 +00:00
whitequark
39605ef551
back.pysim: naming. NFC.
2018-12-18 04:46:36 +00:00
whitequark
65702719e8
back.pysim: fix an off-by-1 in add_sync_process().
2018-12-18 04:43:04 +00:00
whitequark
34b81d0b87
back.pysim: trigger processes waiting on Tick() exactly at clock edge.
2018-12-18 04:37:39 +00:00
whitequark
d6e98fd934
back.pysim: continue running simulator processes until they suspend.
2018-12-18 03:05:16 +00:00
whitequark
c7f9386eab
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
2018-12-17 22:55:39 +00:00
whitequark
8d1639a5a8
hdl, back: add and use SignalSet/SignalDict.
2018-12-17 17:21:29 +00:00
whitequark
f1e390cbc9
back.rtlil: update for Yosys master.
2018-12-17 15:50:43 +00:00
whitequark
850674637a
back.rtlil: implement Array.
2018-12-17 01:15:23 +00:00
whitequark
87cd045ac3
back.rtlil: implement Part.
2018-12-17 01:05:08 +00:00
whitequark
f968678937
back.rtlil: handle reset_less domains.
2018-12-16 23:52:47 +00:00
whitequark
91b7561a00
back.rtlil: extract _StatementCompiler. NFC.
2018-12-16 22:26:58 +00:00
whitequark
b9a0af8bde
back.rtlil: simplify. NFC.
2018-12-16 21:00:00 +00:00
