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  • 2398b7922e back.pysim: Reuse clock simulation commands Stuart Olsen 2020-04-06 22:22:09 -07:00
  • bb1bbcc51a hdl.mem: fix source location of ReadPort.en. whitequark 2020-04-05 02:00:06 +00:00
  • ec8386a797 back.pysim: fix emission of undriven traces to VCD files. whitequark 2020-04-03 05:20:42 +00:00
  • c79caead33 setup: bump pyvcd to ~=0.2. whitequark 2020-04-02 11:17:41 +00:00
  • 995f3a147b Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation Jacob Lifshay 2020-04-01 19:38:14 -07:00
  • 6e1145e2e7 setup: tighten version constraint on Jinja2. whitequark 2020-04-02 01:35:39 +00:00
  • 2d1e12d00c hdl.ast: implement abs() on values. whitequark 2020-03-22 20:50:07 +00:00
  • a0d279850e
         vendor.lattice_ice40: add support for SB_[LH]FOSC as default_clk. WRansohoff 2020-03-20 04:10:48 -04:00
  • 28f5eba9fb vendor: fix typo async_ff_sync Nicolas Robin 2020-03-15 10:33:22 +01:00
  • 7b9c8b440f
         back.pysim: implement modulus operator. Stuart Olsen 2020-03-14 22:22:03 -07:00
  • 4601dd0a69
         Correctly handle resets in AsyncFIFO. awygle 2020-03-14 16:26:07 -07:00
  • 12c79025f3 vendor: fix a few issues in commit 2f8669ca. whitequark 2020-03-12 20:28:41 +00:00
  • 2f8669cad6
         lib.cdc: extract AsyncFFSynchronizer. awygle 2020-03-08 14:37:40 -07:00
  • a14a5723c1 hdl.ast: fix off-by-1 in Initial.__init__(). whitequark 2020-02-19 01:28:14 +00:00
  • ec7aee62ea back.pysim: fix RHS codegen for Cat() and Repl(..., 0). whitequark 2020-02-19 01:21:00 +00:00
  • 377f2d987d back.pysim: optionally allow introspecting generated code. whitequark 2020-02-19 00:56:24 +00:00
  • 5ae87916ec
         nmigen.compat.genlib.cdc: add PulseSynchronizer. awygle 2020-02-15 23:01:44 -08:00
  • fcbabfeefc
         nmigen.lib.cdc: port PulseSynchronizer. awygle 2020-02-15 22:51:53 -08:00
  • 71d9eea4a0 Travis: prune dependencies. whitequark 2020-02-14 06:34:28 +00:00
  • 3fd7fe7880 Travis: test on Python 3.8. whitequark 2020-02-14 06:33:08 +00:00
  • 57b08dbc2c cli: update use of deprecated code. whitequark 2020-02-12 14:42:24 +00:00
  • 8947096eea back.pysim: accept write_vcd(vcd_file=None). whitequark 2020-02-12 14:42:06 +00:00
  • 38aa9fb671 setup: update project URLs. whitequark 2020-02-09 17:03:06 +00:00
  • 4f17cb1ac7 doc: remove outdated files and references to them. whitequark 2020-02-09 14:15:51 +00:00
  • 66f4510c44 README: link to IRC channel. whitequark 2020-02-08 11:00:08 +00:00
  • 36f498e358 README: consolidate requirements in the Installation section. whitequark 2020-02-08 10:54:01 +00:00
  • 3b6727152e test_build_res: fix after commit 3e2ecdf2. whitequark 2020-02-07 00:07:19 +00:00
  • 3e2ecdf2fb build.res,vendor: place clock constraint on port, not net, if possible. whitequark 2020-02-06 23:37:15 +00:00
  • 5888f29c1f xilinx_{7series,ultrascale}: run report_methodology. whitequark 2020-02-06 19:38:21 +00:00
  • 27b47faf16 hdl.ast: add Value.{as_signed,as_unsigned}. whitequark 2020-02-06 18:27:55 +00:00
  • 9301e31b69 test_lib_fifo: define all referenced FSM states. whitequark 2020-02-06 18:10:15 +00:00
  • a1c58633e6 hdl.dsl: make referencing undefined FSM states an error. whitequark 2020-02-06 17:47:46 +00:00
  • 97cc78a3db hdl.ir: type check ports. whitequark 2020-02-06 17:33:41 +00:00
  • 882fddfa96 back.pysim: emit toplevel inputs in VCD files as well. whitequark 2020-02-06 17:19:47 +00:00
  • d3775eedd7 back.pysim: make write_vcd(traces=) actually use those traces. whitequark 2020-02-06 17:07:48 +00:00
  • 3df429703c hdl.dsl: reject name mismatch in m.domains.<name> +=. whitequark 2020-02-06 16:13:59 +00:00
  • 86b57fe6b6 hdl.dsl: type check when adding to m.domains. whitequark 2020-02-06 15:19:16 +00:00
  • 31cd72c0b6 hdl.mem: add synthesis attribute support. whitequark 2020-02-06 14:48:48 +00:00
  • f7abe368a9 hdl.mem: document Memory. whitequark 2020-02-06 13:47:13 +00:00
  • dfcf7938ea hdl.{ast,dsl}: allow whitespace in bit patterns. whitequark 2020-02-04 07:54:54 +00:00
  • a295e3599c hdl.ast: update documentation for Signal. whitequark 2020-02-01 23:15:18 +00:00
  • 49758a3a0c hdl.ast: prohibit shifts by signed value. whitequark 2020-02-01 23:04:25 +00:00
  • cce6b8687b build.plat: align pipeline with Fragment.prepare(). whitequark 2020-02-01 03:24:26 +00:00
  • 6fd7cbad0d hdl.dsl: don't allow inheriting from Module. whitequark 2020-02-01 02:15:45 +00:00
  • afece15001 hdl.ast: warn on unused property statements (Assert, Assume, etc). whitequark 2020-02-01 01:55:23 +00:00
  • 9fb4a4f09e _unused: extract must-use logic from hdl.ir. whitequark 2020-02-01 01:35:05 +00:00
  • 687d3a3df7 hdl.dsl: add missing case width check for Enum values. whitequark 2020-01-31 23:14:16 +00:00
  • a9da9efe5b README: clarify relationship to Migen. whitequark 2020-01-31 21:10:59 +00:00
  • 9964fc6b57 hdl.dsl: make if m.{If,Elif,Else}(...) a syntax error. whitequark 2020-01-31 06:37:45 +00:00
  • 3ac13eb8f9 back.rtlil: don't emit wires for empty signals. whitequark 2020-01-31 03:38:58 +00:00
  • b72c3fc7f6 vendor.lattice_ecp5: support internal oscillator (OSCG). Mike Walters 2020-01-17 16:10:33 +00:00
  • ec3a21939e build.dsl: allow strings to be used as connector numbers. Jaro Habiger 2020-01-26 18:35:41 +01:00
  • 7792a6cd9f vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files Sylvain Munaut 2020-01-20 09:30:49 +01:00
  • c280c7c2af
         Update README. whitequark 2020-01-27 18:13:11 +00:00
  • a7be3b480a hdl.ir: resolve hierarchy conflicts before creating missing domains. whitequark 2020-01-18 10:30:36 +00:00
  • 7cb3095334 hdl.xfrm: transform drivers as well in DomainRenamer. whitequark 2020-01-17 02:13:46 +00:00
  • e18385b613 Remove everything deprecated in nmigen 0.1. whitequark 2020-01-12 13:59:26 +00:00
  • e4e26717be Signal: allow to use integral Enum for reset value. Staf Verhaegen 2020-01-10 13:28:19 +01:00
  • 8184efd612 vendor.intel: fix output enable width for XDR=0 case. schwigi 2020-01-09 11:09:35 +01:00
  • 63902dddb7 build.run: fix indentation. Alain Péteut 2020-01-07 13:39:49 +01:00
  • 476ce15f04 back.rtlil: do not consider unreachable array elements when legalizing. whitequark 2020-01-01 15:26:05 +00:00
  • 318274d5a0 hdl.mem: fix src_loc_at in ReadPort, WritePort. whitequark 2019-12-15 11:46:14 +00:00
  • 67650214b7 hdl.ast: Fix width for unary minus operator on signed argument. Marcin Kościelnicki 2019-12-03 18:33:26 +01:00
  • 7650431996 back.pysim: fix miscompilation of Signal(unsigned) - Signal(signed). whitequark 2019-12-02 18:52:55 +00:00
  • d048f069f8 hdl.ast: actually remove simulator commands. whitequark 2019-12-02 02:23:36 +00:00
  • 72cfdb0c93 vendor.intel: silence meaningless warnings in nMigen files Dan Ravensloft 2019-12-01 00:07:48 +00:00
  • 7df70059d1 back.pysim: redesign the simulator. whitequark 2019-11-22 08:32:41 +00:00
  • f8428ff505 back.rtlil: infer bit width for instance parameters. whitequark 2019-11-27 17:58:42 +00:00
  • 56bb42aff2 hdl.ir: for instance ports, prioritize defs over uses. whitequark 2019-11-26 21:17:12 +00:00
  • f207f3f620 vendor.xilinx_*: Set IOB attribute on cels instead of nets. Jean-François Nguyen 2019-11-18 15:58:39 +01:00
  • 7c322e562a back.rtlil: extend shorter operand of a binop when matching sign. whitequark 2019-11-18 10:39:55 +00:00
  • 834fe3c700 build.plat: in Platform.add_file(), allow adding exact duplicates. whitequark 2019-11-15 23:40:44 +00:00
  • fe400b5dbc test: add tests for build.plat.Platform.add_file. whitequark 2019-11-15 23:35:55 +00:00
  • f8f7d83127 hdl.rec: fix Record.like() being called through a subclass. whitequark 2019-11-09 16:44:01 +00:00
  • dc2a09b8b9 hdl.rec: make Record(name=) keyword-only. Staf Verhaegen 2019-11-09 17:10:36 +01:00
  • 9749c70730 hdl.ir: lower domains before resolving hierarchy conflicts. whitequark 2019-11-07 08:20:27 +00:00
  • e9887780af Improve .gitignore. whitequark 2019-11-02 02:03:14 +00:00
  • 4d6ad28f59 back.verilog: remove $verilog_initial_trigger after proc_prune. whitequark 2019-10-28 10:11:41 +00:00
  • 75d0fcd639 test: use #nmigen: magic comment instead of monkey patch. whitequark 2019-10-26 06:36:54 +00:00
  • 9786d0c0e3 hdl.ir: allow disabling UnusedElaboratable warning in file scope. whitequark 2019-10-26 05:34:00 +00:00
  • 8b05b28f5a back.rtlil: avoid exponential behavior when legalizing Part(). whitequark 2019-10-26 02:01:53 +00:00
  • ffd10e3042 back.rtlil: fix lowering of Part() on LHS to account for stride. whitequark 2019-10-26 01:52:34 +00:00
  • 51269ad4a0 hdl.ast: simplify {bit,word}_select with constant offset. whitequark 2019-10-26 00:09:53 +00:00
  • 61e6267daf Explicitly restrict prelude imports. whitequark 2019-10-21 10:39:21 +00:00
  • 9fba5ccb51 compat.fhdl.specials: fix argument parsing compatibility. whitequark 2019-10-17 07:54:36 +00:00
  • fb90043460 lib.io: use keyword-only arguments in Pin(). whitequark 2019-10-16 19:50:04 +00:00
  • 045f5e19a2 setup: fix commit 5198d99b. whitequark 2019-10-16 14:24:13 +00:00
  • 07b3510218 verilog: fix yosys version error message Sebastien Bourdeauducq 2019-10-16 13:10:19 +08:00
  • 58300d8eb6 back.verilog: fix Yosys version check. whitequark 2019-10-16 02:25:35 +00:00
  • 5198d99b5e setup: don't append local version for tags. whitequark 2019-10-15 04:04:18 +00:00
  • 1bb3fa861c vendor.lattice_ice40: fix commit 88649def. whitequark 2019-10-14 15:55:11 +00:00
  • b3a8a43152 vendor.lattice_{ice40,ecp5}: fix typo. whitequark 2019-10-13 22:17:46 +00:00
  • 88649defda vendor.lattice_ice40: use pcf files instead of pre-pack Python scripts. whitequark 2019-10-13 21:56:40 +00:00
  • be6c16d0a2 build.plat: batch files use EQU, not EQ. whitequark 2019-10-13 21:45:56 +00:00
  • 2f9dab361f {,_}tools→{,_}utils whitequark 2019-10-13 18:53:38 +00:00
  • ccd28b40c2 vendor.lattice_{ice40,ecp5}: emit Verilog as well, for debugging. whitequark 2019-10-13 18:04:33 +00:00
  • b8b8e0ba0b build.plat: fold emit_prelude() into emit_commands(). whitequark 2019-10-13 13:57:48 +00:00
  • a783e4645d Refactor build script toolchain lookups. Emily 2019-10-13 14:53:24 +01:00
  • 29253295ee hdl.ir: allow ClockSignal and ResetSignal in ports. whitequark 2019-10-13 03:39:56 +00:00
  • 722b3879f4 hdl.ir: cast instance port connections to Values. whitequark 2019-10-13 03:19:17 +00:00