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  • 13650acbbc compat.fhdl.decorators: improve backwards compatibility. whitequark 2019-10-13 01:38:09 +0000
  • d2c4c7c060 compat.fhdl.bitcontainer: update Value.wrap call. whitequark 2019-10-13 01:37:11 +0000
  • 1334bd6a8b doc: bring COMPAT_SUMMARY up to date. whitequark 2019-10-12 23:15:09 +0000
  • 1387e2f9df compat.genlib.fsm: add migration warning. whitequark 2019-10-12 22:48:08 +0000
  • dbddddff17 compat.fhdl.decorators: add migration warnings. whitequark 2019-10-12 22:44:12 +0000
  • a7e3b80409 hdl.ast: rename Slice.end back to Slice.stop. whitequark 2019-10-12 22:40:30 +0000
  • 77118fb9c9 compat.fhdl.structure: remove SPECIAL_* constants. whitequark 2019-10-12 22:35:43 +0000
  • da48c05bdf _tools: extract most utility methods to a private package. whitequark 2019-10-12 22:27:43 +0000
  • a97003d57a back.rtlil: fix DeprecationWarning. NFC. Jean-François Nguyen 2019-10-12 23:44:39 +0200
  • b90687c988 Rename remaining wrap methods to cast. whitequark 2019-10-11 13:28:26 +0000
  • a658cb2bbf hdl.ast: deprecate shapes like (1, True) in favor of signed(1). whitequark 2019-10-11 13:22:08 +0000
  • 706bfaf5e1 hdl.ast: deprecate Signal.{range,enum}. whitequark 2019-10-11 13:07:42 +0000
  • 6aabdc0a73 hdl.ast: add an explicit Shape class, included in prelude. whitequark 2019-10-11 12:52:41 +0000
  • db960e7c30 Consistently use {!r}, not '{!r}' in diagnostics. whitequark 2019-10-11 11:47:42 +0000
  • fa1e466a65 hdl.ast: Operator.{op→operator} whitequark 2019-10-11 11:37:26 +0000
  • 7ff4c6ce43 hdl.ast: simplify enum handling. whitequark 2019-10-11 11:16:00 +0000
  • d72d4a55fd hdl.ast: Value.{wrap→cast} whitequark 2019-10-11 10:49:34 +0000
  • 9fe27a15ad vendor.xilinx_ultrascale: new supported family. whitequark 2019-10-10 16:35:48 +0000
  • bfd4538df0 xilinx_7series: add grade platform property. whitequark 2019-10-10 16:25:10 +0000
  • ef741594b5 vendor.lattice_machxo2: new supported family. whitequark 2019-10-10 15:33:01 +0000
  • a7cc88f3d4 vendor: yosys is a required tool for all Verilog-based flows. whitequark 2019-10-10 14:38:09 +0000
  • 730eff5d57 README: add device support matrix. whitequark 2019-10-10 00:50:01 +0000
  • 8021e2dd76 vendor.intel: add Quartus support. whitequark 2019-08-21 22:14:33 +0000
  • 7dfd7fb12a examples: update blinky, add some explanatory text about domains. whitequark 2019-10-09 23:19:19 +0000
  • 7257c20a6a build.plat: elaborate result of create_missing_domain() against platform. whitequark 2019-10-09 21:16:14 +0000
  • 27a32f0218 build.plat: don't create default sync domain as reset-less. whitequark 2019-10-09 20:44:07 +0000
  • b9e57fd67b build.plat,vendor: always synchronize reset in default sync domain. whitequark 2019-10-09 20:02:33 +0000
  • 2512a9a12d back.rtlil: don't crash legalizing values with no branches. whitequark 2019-10-06 08:52:49 +0000
  • 964c67453f back.rtlil: avoid unsoundness for division by zero. whitequark 2019-10-04 07:56:06 +0000
  • de34728bf8 hdl.ast: prohibit signed divisors. whitequark 2019-10-04 07:49:24 +0000
  • 751ae33fe1 build.dsl: accept Pins(invert=True). whitequark 2019-10-03 02:44:43 +0000
  • 9458de2079 hdl.ast: don't crash on Mux(<bool>, ...). whitequark 2019-10-02 08:24:37 +0000
  • d139f340b3 back.rtlil: don't cache wires for legalized switch tests. whitequark 2019-10-02 07:51:49 +0000
  • d3f7cc8ed2 back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't need to match. whitequark 2019-10-02 03:50:20 +0000
  • 3a1dae591b back.rtlil: it is not necessary to match binop operand width. whitequark 2019-10-02 03:38:58 +0000
  • 905920aa76 rpc: add public Records as module ports. Jean-François Nguyen 2019-09-30 00:12:17 +0200
  • 52f36025a9 rpc: add support for Yosys RPC protocol. whitequark 2019-09-27 02:35:45 +0000
  • 1621ceb65a hdl.ast: actually implement the // operator. whitequark 2019-09-28 19:33:24 +0000
  • 450d7efdf2 hdl.dsl: add a diagnostic for m.d.submodules += .... whitequark 2019-09-28 17:50:24 +0000
  • a02e3750bf hdl.mem: remove WritePort(priority=) argument. whitequark 2019-09-28 01:29:56 +0000
  • e3a1d05f23 back.rtlil: fix handling of certain nested arrays. whitequark 2019-09-24 18:32:26 +0000
  • 53bb4300a3 build.plat: strip internal attributes from Verilog output. whitequark 2019-09-24 14:54:22 +0000
  • f87c00e6c3 build.plat,lib.cdc,vendor: unify platform related diagnostics. NFC. whitequark 2019-09-24 14:14:45 +0000
  • 0858b8bf6c lib.cdc: specify maximum input delay in seconds. whitequark 2019-09-24 12:30:02 +0000
  • b43d2d36e8 vendor.xilinx_spartan_3_6: explain why ASYNC_REG is used. NFC. whitequark 2019-09-24 12:22:29 +0000
  • d14366450b vendor.lattice_ecp5: correct a typo in tristate buffer generation Kate Temkin 2019-09-24 00:55:00 -0600
  • f3a8880cb8 vendor.xilinx_7series: apply false path / max delay constraints. Darrell Harmon 2019-09-23 18:47:54 -0600
  • da53048ad4 vendor.xilinx_7series: simplify. NFC. whitequark 2019-09-23 20:27:42 +0000
  • 6d8590a391 vendor.xilinx_7series: override reset synchronizer. whitequark 2019-09-23 20:15:29 +0000
  • 22da78ca28 lib.cdc: add diagnostic checks for synchronization stage count. whitequark 2019-09-23 19:38:21 +0000
  • 52e761dc33 lib.cdc: expand ResetSynchronizer documentation. whitequark 2019-09-23 19:31:23 +0000
  • 86f0f12b58 lib.cdc: avoid modifying synchronizers in their elaborate() method. whitequark 2019-09-23 16:42:44 +0000
  • 51f03bb509 vendor.xilinx_spartan_3_6: override reset synchronizer. Darrell Harmon 2019-09-23 10:28:15 -0600
  • c16f5ecf34 README: add a section on migrating from Migen. whitequark 2019-09-23 16:01:59 +0000
  • 8deb13cea3 lib.cdc: MultiReg→FFSynchronizer. whitequark 2019-09-23 14:17:44 +0000
  • b227352258 hdl.ast: cast Mux() selector to bool if it is not a 1-bit value. whitequark 2019-09-23 13:39:31 +0000
  • 7777b7b98c back.rtlil: give predictable names to anonymous subfragments. whitequark 2019-09-23 12:48:02 +0000
  • fd625619f1 lib.fifo: handle depth=0, elaborating to a dummy FIFO with no logic. whitequark 2019-09-23 12:27:59 +0000
  • bc53bbf564 hdl.mem,lib.fifo: use keyword-only arguments for memory geometry. whitequark 2019-09-23 11:18:01 +0000
  • 1aeb11d7e3 hdl.mem: simplify. NFC. whitequark 2019-09-23 11:16:29 +0000
  • 649444449d hdl.ast: make Signal(name=) a keyword-only argument. whitequark 2019-09-23 11:08:43 +0000
  • 2da0133d52 lib.fifo: change FIFOInterface() diagnostics to follow Memory(). whitequark 2019-09-23 11:03:50 +0000
  • ca6b1f2f1c lib.fifo: round up AsyncFIFO{,Buffered} depth to lowest valid value. whitequark 2019-09-23 10:57:30 +0000
  • a57b76fb5d lib.fifo: make simulation read() and write() functions compat-only. whitequark 2019-09-23 08:45:58 +0000
  • 1976310bf0 hdl.rec: fix using Enum subclass as shape if direction is specified. whitequark 2019-09-22 17:23:32 +0000
  • 4c582ef609 hdl.rec: allow using Enum subclass as shape. whitequark 2019-09-22 15:16:36 +0000
  • 6414c80b82 lib.fifo: add more compatibility shims. whitequark 2019-09-22 11:56:03 +0000
  • 59acd5d5a5 vendor.lattice_ice40: fix required tool list for iCECube2. NFC. whitequark 2019-09-22 07:18:37 +0000
  • 5f9b8ec1eb vendor.lattice_ecp5: simplify quoting. NFC. whitequark 2019-09-22 07:17:12 +0000
  • ee1ad2daf1 build.plat: restrict design names to alphanumeric to avoid quoting issues. whitequark 2019-09-22 06:57:28 +0000
  • 3d62dac1cb vendor.lattice_ice40: add iCECube support. whitequark 2019-09-21 14:27:35 +0000
  • 8050cfaa98 build.res: simplify clock constraints. whitequark 2019-09-21 14:12:29 +0000
  • 07a82ed70e build.plat: NMIGEN_<toolchain>_env→NMIGEN_ENV_<toolchain> whitequark 2019-09-21 12:23:53 +0000
  • 2dc6ae4ac5 lib.fifo: update docs. NFC. whitequark 2019-09-21 06:53:39 +0000
  • a13a21cbd6 hdl.ast: update docs. NFC. whitequark 2019-09-21 06:53:13 +0000
  • f6f0a7b692 lib.fifo: simplify. NFC. whitequark 2019-09-21 06:09:30 +0000
  • a1bc2bbeb0 lib.fifo: fix doc typo. NFC. whitequark 2019-09-20 19:50:43 +0000
  • f9b9c17a16 lib.fifo: work around Yosys issue with handling of \TRANSPARENT. whitequark 2019-09-20 19:38:42 +0000
  • 4b3a068b15 hdl.mem: use 1 as reset value for ReadPort.en. whitequark 2019-09-20 19:36:19 +0000
  • 91ef2f58e3 vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals. whitequark 2019-09-20 16:11:01 +0000
  • 378e924280 hdl.ast: rename nbits to width. whitequark 2019-09-20 15:35:55 +0000
  • af7224de5d vendor.xilinx_{7series,spartan3_6}: specialize MultiReg. Darrell Harmon 2019-09-20 09:13:27 -0600
  • f2550021c3 setup: improve repository detection. Emily 2019-09-20 14:48:08 +0100
  • 6f12272533 setup: add setuptools dependency. Emily 2019-09-20 14:48:03 +0100
  • 276e9c2fad test.test_lib_fifo: fix typo. whitequark 2019-09-20 11:53:05 +0000
  • 7f6b3f93f5 back.pysim: fix simulation of Value.xor(). whitequark 2019-09-20 10:12:59 +0000
  • 4777a7b3a2 hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns. whitequark 2019-09-16 18:59:28 +0000
  • e8f79c5539 hdl.ast: add Value.matches(), accepting same language as Case(). whitequark 2019-09-14 21:06:12 +0000
  • f292a1977c hdl.dsl: improve error messages for Case(). whitequark 2019-09-14 20:46:10 +0000
  • 32310aecad hdl.ast: add Value.xor, mapping to $reduce_xor. whitequark 2019-09-13 14:28:43 +0000
  • b23a9794a4 hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}. whitequark 2019-09-13 13:14:52 +0000
  • bdb70ad45f lib.fifo: adjust for new CDC primitive conventions. whitequark 2019-09-12 20:01:28 +0000
  • da4b810fe1 lib.fifo: adjust properties to have consistent naming. whitequark 2019-09-12 19:51:01 +0000
  • 9ea3ff7ae2 build.plat: bypass tool detection if NMIGEN_*_env is set. whitequark 2019-09-12 21:56:48 +0000
  • c8f8c09f29 vendor.xilinx_7series: Vivado requires bash on *nix as well. whitequark 2019-09-12 21:49:08 +0000
  • 42805ad959 hdl.mem: use keyword-only arguments as appropriate. whitequark 2019-09-12 20:03:48 +0000
  • b92e967b78 lib.fifo: make fwft a keyword-only argument. whitequark 2019-09-12 19:36:45 +0000
  • 1c091e67a4 lib.fifo: remove SyncFIFO.replace. whitequark 2019-09-12 19:14:56 +0000
  • 2c34b1f947 README: update Yosys version requirement. whitequark 2019-09-12 14:33:38 +0000
  • 2d2ab6e09d lib.cdc: make domain properties private. whitequark 2019-09-12 13:54:48 +0000