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Author SHA1 Message Date
Catherine 5a17f94fdc hdl.rec: deprecate in favor of lib.data and lib.wiring. 
Tracking #879.
 2023-09-01 04:20:16 +00:00
Catherine cd4ea96bd1 Implement RFC 19: Remove amaranth.lib.scheduler 2023-09-01 00:56:12 +00:00
Catherine 44d5fac01c lib.wiring: fix equality of FlippedSignature with other object. 
Fixes #882.
 2023-08-31 19:26:07 +00:00
Catherine f95fe45186 Implement RFC 22: Add ValueCastable.shape(). 
Fixes #794.
Closes #876.
 2023-08-23 10:48:48 +00:00
Catherine 4ffadff20d lib.wiring: implement amaranth-lang/rfcs#2. 
Co-authored-by: Charlotte <charlotte@lottia.net>
 2023-08-22 16:22:09 +00:00
Marcelina Kościelnicka f6c38061ff lib.data: fix Layout.const masking for signed fields. 
Fixes #846.
 2023-07-22 00:35:42 +00:00
Catherine d1ca9c46a5 lib.data: allow Const as value of Layout.const(...) field. 
Fixes #838.
 2023-07-18 14:35:57 +00:00
Catherine 385b10d743 lib.data: improve diagnostics for field access on array layout view. 
Fixes #837.
 2023-07-18 14:35:49 +00:00
Charlotte 7e438180e0 lib.enum: allow empty enums. 2023-07-04 10:28:22 +00:00
Adam Greig 45b9730786 Implement RFC 6: CRC Generator 
See amaranth-lang/rfcs#6 and #681.
 2023-06-29 02:42:47 +00:00
Charlotte fd4e25df42 test_sim: failing test case. 2023-06-29 01:28:44 +00:00
Catherine b77e33f16a Drop support for Python 3.7. 2023-06-28 14:50:30 +00:00
Charlotte 59a83cf7eb test_sim: add failing test case for bitwise binary ops. 
See https://github.com/amaranth-lang/amaranth/pull/826#event-9609577585.
 2023-06-24 06:34:48 +00:00
Charlotte 4ec9cbbffe sim._pyrtl: py3.12+: convert to int before bitwise negating. 
Amaranth bitwise negation `~` compiles to Python bitwise negation `~` in
simulation; the same holds for comparison operators such as `==`. Thus
an expression such as `~(a == b)` in simulation will compile to Python
that takes the bitwise negation of the comparison result, which will be
an actual bool.

On 3.12, the result is a `DeprecationWarning` emitted only at simulation
run-time.

When negating in simulation, coerce the value to an int. `mask` is
sufficient as we do no further arithmetic here.
 2023-06-22 17:37:30 +00:00
Charlotte 63f9976267 tests.test_sim.SimulatorRegressionTestCase.test_bug_588: fix for Windows paths. 2023-06-22 03:52:55 +00:00
Charlotte d218273b9b hdl.ast: deprecate Repl and remove from AST; add Value.replicate. 2023-06-22 03:52:55 +00:00
Marcelina Kościelnicka b1cce87630 hdl.ast: make Value.__abs__ return unsigned shape. 2023-06-07 23:20:26 +00:00
Marcelina Kościelnicka 1d5e090580 hdl.ast: fix shape for subtraction. 
Fixes #813.
 2023-06-07 12:34:30 +00:00
Marcelina Kościelnicka 3180a17fd9 hdl.ast: fix Slice validation. 
Fixes #810.
 2023-06-07 12:26:36 +00:00
Marcelina Kościelnicka c7984463c7 hdl.ast: fix range handling in Shape.cast. 
Fixes #803.
 2023-06-07 12:26:30 +00:00
Marcelina Kościelnicka a6e33abc5f hdl.ast: guard rotate_* against 0-width values. 
Fixes #808.
 2023-06-07 12:12:24 +01:00
Marcelina Kościelnicka 656db317d2 hdl.ast: fix signed Const normalization. 
Fixes #805.
 2023-06-07 11:22:52 +01:00
Catherine a4402b507f hdl.dsl: py3.12+: turn off heuristic warning on ~True and ~False. 
There is now an upstream deprecation warning for the same.
We don't have to duplicate it.
 2023-06-02 13:45:15 +01:00
Catherine 58b8acac0d _toolchain.cxx: remove. 
This is causing issues on Python 3.12 and in any case should be
based on the Python `ziglang` package instead of this cursed
setuptools hack.
 2023-06-02 13:45:15 +01:00
Marcelina Kościelnicka c343e879d3 tracer: fix STORE_DEREF handling, add EXTENDED_ARG support. 
This fixes the following issues:

- on Python 3.10 and earlier, storing to free variables is now handled
  correctly
- on Python 3.11, `_varname_from_oparg` is now used, fixing problems
  with cell variables that are also arguments
- on all supported versions, EXTENDED_ARG is now parsed, ensuring proper
  handling for long functions

Fixes #792.
 2023-06-01 19:18:43 +01:00
Catherine 2a45d0e9ad lib.data: warn if a field is shadowed by an attribute of the view. 
Fixes #796.
 2023-05-31 13:27:20 +01:00
Catherine f96604f667 lib.data: make all layouts immutable. 
This is actually an existing correctness requirement (for the similar
reasons that ValueCastable.as_value() must always return the same
value every time) that for some reason wasn't respected.
 2023-05-23 23:19:29 +01:00
Catherine 7d99981d57 Implement RFC 15: Lifting shape-castable objects. 
See amaranth-lang/rfcs#15 and #784.

Note that this RFC breaks the existing syntax for initializing a view
with a new signal. Instances of `View(layout)` *must* be changed to
`Signal(layout)`.
 2023-05-15 19:42:12 +01:00
Catherine 54d5c4c047 Implement RFC 9: Constant initialization for shape-castable objects. 
See amaranth-lang/rfcs#9 and #771.
 2023-05-12 23:41:57 +01:00
Catherine 7166455a6a lib.data: implement extensibility as specified in RFC 8. 
See amaranth-lang/rfcs#8 and #772.
 2023-05-12 20:03:08 +01:00
Catherine 4398575322 lib.enum: accept any const-castable expression as member value. 
This behavior was introduced by amaranth-lang/rfcs#4. See #755.
 2023-05-12 16:39:02 +01:00
Catherine bf8bbb0f63 lib.enum: check member value shapes before subclassing. NFCI 
This commit is a preparation for accepting const-castable expressions
as enum member values.

See #755.
 2023-05-12 16:39:02 +01:00
Arusekk 5f094a23eb hdl.ast: Test *Castable subclasses on definition. 
The __init_subclass__ method fires on class definition rather than use.
It also has the bonus impact that no __new__ method is defined, so the
classes can be correctly detected as mix-in classes by modules such as
enum.
 2023-03-21 23:22:47 +00:00
Catherine 80343d1c4c hdl.ast: warn on fencepost error in Signal(range(x), reset=x). 
Also, relax the language reference inset from "warning" to "note"
since this is no longer something developers have to keep in mind
explicitly.
 2023-03-13 20:38:41 +00:00
Catherine ae1aeff0f2 lib.data: at most one Union field can have annotation with a default. 2023-03-04 09:34:50 +00:00
Catherine 16be75e02c lib.data: fix typo. 2023-03-03 09:03:53 +00:00
Catherine 0c4fda92fe hdl.ast: accept any constant-castable expression in Signal(reset=). 
See amaranth-lang/rfcs#4.

This functionality was not explicitly specified in the RFC but it
falls under "anywhere an integer or an enumeration is accepted".
 2023-03-03 06:22:56 +00:00
Catherine f77a335abf lib.enum: change shape mismatch warning category to SyntaxWarning. 2023-03-03 06:14:53 +00:00
Catherine c1b9c64e10 lib.data: ignore Python typing annotations in aggregate base class. 2023-03-03 03:45:12 +00:00
Catherine 14e73a73de hdl.ast: do not cast comparand to shape in Shape.__eq__. 
This doesn't match how other Python comparison operators work.
E.g. `1 == int("1")` but `1 != "1"`.
 2023-02-28 15:52:50 +00:00
Catherine 35561ea11a lib.data: improve reset value handling for Union. 
* Reject union initialization with more than one reset value.
* Replace the reset value specified in the class definition with
  the one provided during initalization instead of merging.
 2023-02-28 15:38:20 +00:00
Catherine c7ef05c894 lib.data: improve annotation handling for Struct and Union. 
* Annotations like `s: unsigned(4) = 1` are recognized and
  the assigned value is used as the reset value for the implicitly
  created `Signal`.
* Base classes inheriting from `Struct` and `Union` without
  specifying a layout are recognized.
* Classes that both inherit from a base class with a layout and
  specify a layout are rejected.
 2023-02-28 15:38:18 +00:00
Catherine 0ee5de036c hdl.ast: deprecate Sample, Past, Rose, Fell, Stable. 
See #526.
 2023-02-28 14:30:04 +00:00
Catherine 57612f1dce lib.enum: add Enum wrappers that allow specifying shape. 
See #756 and amaranth-lang/rfcs#3.
 2023-02-28 13:00:41 +00:00
Catherine ef2e9fa809 hdl.ast: Value.matches() with no arguments should return C(1). 
The behavior of the following must be always the same:
- `with m.Switch(v): with m.Case(*pats):`
- `with m.If(v.matches(*pats)):`
 2023-02-28 09:09:27 +00:00
Catherine 58721ee4fe hdl: implement constant-castable expressions. 
See #755 and amaranth-lang/rfcs#4.
 2023-02-27 22:38:38 +00:00
Catherine bef2052c1e hdl.ast: implement Value.__pos__. 2023-02-27 22:31:17 +00:00
Catherine fcc4f54367 lib.data: make Field() immutable. 
Mutability of Field isn't specified by the RFC and can cause issues
if the objects stored in Layout subclasses are mutated. There isn't
any reason to do that (the subclasses themselves are mutable and
handle that correctly), so disallow it.
 2023-02-21 17:58:28 +00:00
Catherine 7e3e10e733 lib.data: implement RFC 1 "Aggregate data structure library". 
See amaranth-lang/rfcs#1.
 2023-02-15 10:10:01 +00:00
Catherine 5a79c351e3 Remove features deprecated in version 0.3. 2023-01-31 21:38:27 +00:00
Catherine 7044e09110 hdl.ast: remove Shape<>tuple comparisons. 
See #691.

I missed this in commit 29502442.
 2023-01-31 15:23:06 +00:00
Catherine 29502442fb hdl.ast: remove Shape<>tuple casts. 
Closes #691.
 2023-01-31 12:58:29 +00:00
Arusekk de6b69370f hdl.ast: Do not warn on int Enums in Cat. 
This aligns with the behavior for plain Enums.
 2023-01-22 23:40:39 +00:00
Arusekk 58a0c68279 hdl.ast: allow typed int enums in Value.cast. 2023-01-22 23:40:39 +00:00
Catherine da26f1c915 hdl,back,sim: accept .as_signed() and .as_unsigned() on LHS. 
These operators are ignored when they are encountered on LHS, as
the signedness of the assignment target does not matter in Amaranth.
.as_signed() appears on LHS of assigns to signed aggregate fields.
 2022-09-24 07:19:47 +00:00
Catherine bf16acf2f0 hdl.ast: implement ShapeCastable (like ValueCastable). 
Refs #693.
 2022-09-24 07:19:03 +00:00
Catherine 0723f6bac9 hdl.ast: recursively cast ValueCastable objects to values. 2022-09-24 07:18:57 +00:00
Bastian Löher 02364a4fd7 sim: Fix clock phase in add_clock having to be specified in ps. 2022-02-04 16:46:52 +00:00
Irides 538c14116c sim.pysim: use "bench" as a top level root for testbench signals. 
Fixes #561.
 2021-12-16 15:46:05 +00:00
Catherine 847e46927b back.{verilog,rtlil}: fix commit d83c4a1b. 
The `ports` argument has been passed implicitly, via `**kwargs`, and
that was broken during the deprecation.

Closes #659.
 2021-12-14 10:47:04 +00:00
Irides d83c4a1b21 back.{rtlil,verilog}: deprecate implicit ports. 
Fixes #630.
 2021-12-13 12:21:44 +00:00
modwizcode 1ee2482c6b sim: represent time internally as 1ps units 
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.

Fixes #535.
 2021-12-13 08:15:11 +00:00
whitequark 7c161957bf build.dsl: check type of resource number. 
Fixes #599.
 2021-12-11 13:37:15 +00:00
whitequark 7e2b72826f sim.core: warn when driving a clock domain not in the simulation. 
Closes #566.
 2021-12-11 13:22:24 +00:00
whitequark ac13a5b3c9 sim._pyrtl: reject very large values. 
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
 2021-12-11 13:00:46 +00:00
whitequark 599615ee3a hdl.ir: reject elaboratables that elaborate to themselves. 
Fixes #592.
 2021-12-11 12:40:05 +00:00
whitequark 66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names. 
Closes #595.
 2021-12-11 11:12:25 +00:00
whitequark b452e0e871 hdl.ast: support division and modulo with negative divisor. 
Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
 2021-12-11 10:25:48 +00:00
whitequark 44b8bd29af hdl.ast: warn on bare integer value used in Cat()/Repl(). 
Fixes #639.
 2021-12-11 08:18:33 +00:00
whitequark de7c9acb19 _utils: don't crash trying to flatten() strings. 
Fixes #614.
 2021-12-11 07:39:35 +00:00
whitequark 909a3b8be7 Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
whitequark 11914a1e67 hdl.ast: improve interaction of ValueCastable with custom __getattr__. 
Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.
 2021-10-03 20:28:07 +00:00
whitequark e88d283ed3 hdl.ast: simplify Mux implementation. 2021-10-02 14:18:02 +00:00
whitequark 65499d5c45 hdl.ast: add tests for casting bare integers in {Cat,Repl}. 2021-10-02 13:18:11 +00:00
Robin Ole Heinemann b38b2cdad7 test.test_hdl_ast.OperatorTestCase: remove duplicate test_bool 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 2d85f888d6 tests: rename tests with duplicate names 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann b93a54ac58 tests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 25caf4045b *: remove unused imports 2021-05-18 20:18:55 +00:00
Thomas Watson d09dedfb48 tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements 2021-05-11 02:41:32 +00:00
Thomas Watson 7443f89200 hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements 2021-05-11 02:41:32 +00:00
whitequark c30dcea24d hdl.ast: handle int subclasses as slice start/stop values. 
Fixes #601.
 2021-03-18 23:52:23 +00:00
Robin Ole Heinemann 9af8201727 lib.fifo.AsyncFIFOBuffered: fix output register accounting 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann 2a7a3aef87 lib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann d15705cf4f lib.fifo: use proper clock domains in AsyncFIFO tests 2021-01-06 01:05:46 +00:00
whitequark 818c8bc464 hdl.ast: normalize case values to two's complement, not signed binary. 
This was an especially insidious bug because the minus character is
valid in case values but has a completely different meaning (wildcard
rather than sign).

Fixes #559.
 2020-12-12 12:42:12 +00:00
awygle c1ed90807b
nmigen.hdl.rec: restore Record.shape(). 
This method was lost in commit abbebf8e.
 2020-11-17 19:36:58 +00:00
Marcelina Kościelnicka 44318149e0
sim._pyrtl: mask Mux selection operand. 
Otherwise it behaves funny when it's eg. the result of operator ~.
 2020-11-14 15:22:34 +00:00
whitequark d6da4c257b build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files. 
This function was added in commit 20553b14 in the wrong place, with
the wrong name, and without tests. Fix all that.
 2020-11-10 05:30:30 +00:00
awygle ea94c9cc45
hdl.rec: proxy operators correctly. 
Commit abbebf8e used __getattr__ to proxy Value methods called on 
Record. However, that did not proxy operators like __add__ because
Python looks up the special operator methods directly on the class
and does not run __getattr__ if they are missing.

Instead of using __getattr__, explicitly enumerate and wrap every
Value method that should be proxied. This also ensures backwards
compatibility if more methods are added to Value later.

Fixes #533.
 2020-11-09 20:20:25 +00:00
whitequark bde37fe2f2 hdl.ast: deprecate UserValue in favor of ValueCastable. 
Closes #527.
 2020-11-06 02:21:53 +00:00
whitequark 10fd5cff4b CI: run testsuite with -Werror. 2020-11-06 01:38:03 +00:00
awygle abbebf8efe
hdl.rec: migrate Record from UserValue to ValueCastable. 
Closes #528.
 2020-11-06 01:10:39 +00:00
awygle 06c734992f
hdl.ast: implement ValueCastable. 
Closes RFC issue #355.
 2020-11-06 00:20:54 +00:00
Jaro Habiger b15f0562a6 lib.fifo: fix {r,w}_level in AsyncFIFOBuffered 2020-11-03 09:34:12 +00:00
Jaro Habiger c7014f84ea lib.fifo: fix level on fifo full 2020-11-03 09:20:30 +00:00
Robin Ole Heinemann 05decc43b2 lib.fifo.AsyncFFSynchronizer: check input and output signal width 2020-10-28 00:08:38 +00:00
whitequark e3207b74f4 build.dsl: clean up inversion logic. 
* Add invert= argument to DiffPairs() constructor, like in Pins().
  * Make PinsN() and DiffPairsN() pass invert= to the corresponding
    construtor instead of mutating.
 2020-10-26 19:50:21 +00:00
anuejn d8273a15c3
lib.fifo.AsyncFIFO: fix incorrect latency of r_level. 
Co-authored-by: Andrew Wygle <awygle@gmail.com>
 2020-10-24 14:58:23 +00:00
anuejn ca6fa036f6
tests: make spec directory name unique per test method. 2020-10-22 21:38:44 +00:00
whitequark df70aae887 sim._pyrtl: sign extend RHS of assignment. 
Fixes #502.
 2020-10-22 16:08:38 +00:00