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102 commits

Author SHA1 Message Date
Alain Péteut
b67f5cfa65 vendor.xilinx_7series: read extra .xdc files. 2019-07-02 08:23:37 +00:00
whitequark
6454378fe7 vendor.lattice_ice40: fix instance of negedge FF due to a typo. 2019-06-28 07:05:20 +00:00
whitequark
f60ceb349b vendor.xilinx_{spartan6,7series}: speedgrade→speed. 
For consistency with ECP5.
 2019-06-25 15:51:52 +00:00
whitequark
0a145ed2d9 vendor.lattice_ecp5: implement. 
Note that because of issues with Yosys and nextpnr, it is not yet
possible to use either SDR or DDR I/O.
 2019-06-25 15:48:07 +00:00
whitequark
23ed888857 vendor.lattice_ice40: use different --package for 4k devices. 2019-06-19 06:09:08 +00:00
Jean-François Nguyen
b3c5ff7e95 vendor.xilinx_7series: fix IOB packing. 2019-06-17 20:48:46 +00:00
whitequark
3fc5f170e6 vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly. 
Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.
 2019-06-17 15:47:56 +00:00
whitequark
2a8e7bc6f2 vendor.xilinx_{7series,spartan6}: cleanup. NFC. 
Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.
 2019-06-17 15:47:56 +00:00
whitequark
8b34602d91 vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly. 
Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.
 2019-06-17 15:47:56 +00:00
whitequark
70bbfecf6d vendor.lattice_ice40: never place an inverter on global buffer output. 
This would make `pin.i` not a global network anymore, which is likely
undesirable if an explicit Attrs(GLOBAL=1) is specified.
 2019-06-14 20:44:02 +00:00
Jean-François Nguyen
01a3101fd3 vendor.xilinx_7series: implement inverters. 2019-06-13 15:14:09 +00:00
Jean-François Nguyen
412781e0c3 vendor.xilinx_spartan6: implement DDR I/O buffers and inverters. 2019-06-13 15:13:31 +00:00
whitequark
6beba3a48b Simplify code by using Signal.like(name_suffix="..") appropriately. 2019-06-12 22:28:45 +00:00
Jean-François Nguyen
3b303c3334 vendor.xilinx_7series: implement DDR I/O buffers. 2019-06-12 19:55:10 +00:00
whitequark
d3ed390b9d vendor.lattice_ice40: fix typo. 2019-06-12 17:38:14 +00:00
whitequark
efb2d773c3 build.{dsl,res,plat}: add PinsN and DiffPairsN. 2019-06-12 14:42:39 +00:00
Jean-François Nguyen
d5ba26b174 vendor.xilinx_spartan6: implement. 2019-06-07 08:58:41 +00:00
Jean-François Nguyen
2b3a0e9fa0 vendor.xilinx_7series: fix typos. 2019-06-07 07:33:20 +00:00
Jean-François Nguyen
f26e612899 vendor.xilinx_7series: implement. 2019-06-06 13:22:15 +00:00
whitequark
c9879c795b build.{dsl,res,plat}: apply clock constraints to signals, not resources. 
This adds the Clock() build DSL element, and adds a resource manager
function add_clock_constraint() that takes a Pin or a Signal.
Note that not all platforms, in particular not any nextpnr platforms
at the moment, can add constraints on arbitrary signals.

Fixes #86.
 2019-06-05 08:52:30 +00:00
whitequark
ab3f103e5a build.dsl: replace extras= with Attrs(). 
This change proved more tricky than expected due to downstream
dependencies, so it also includes some secondary refactoring.
 2019-06-05 07:02:08 +00:00
whitequark
c52cd72d3e Typos and style fixes. NFC. 2019-06-05 02:48:41 +00:00
whitequark
452c4b380b vendor.lattice_ice40: normalize device names. 
Right now the device name in the board file is just the option
nextpnr uses, but that's overnormalized and doesn't quite match
the chip names used elsewhere. It is even worse for ECP5 in terms
of mismatch with chip names, and for ECP5 we need to support other
toolchains as well, so let's handle this uniformly everywhere.
 2019-06-04 16:09:08 +00:00
whitequark
1b54eb80da vendor.board: split off into nmigen-boards package. 
The iCE40 programmers are also moved, since they're board-specific.
(It looks like iceprog isn't, but it only works with Lattice
evaluation kits.)

Fixes #80.
 2019-06-04 09:52:33 +00:00
whitequark
316ba10207 build.run: simplify using build products locally, e.g. for programming. 2019-06-04 09:13:24 +00:00
whitequark
2763b403f1 build.res: simplify emission of port constraints on individual bits. 2019-06-04 08:39:03 +00:00
whitequark
9f643ce005 Clean up imports. 
This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.
 2019-06-04 08:18:50 +00:00
whitequark
c89c2ce941 vendor.board.tinyfpga_bx: clk16 pin does not have a global buffer. 
Fixes #82.
 2019-06-04 06:43:10 +00:00
whitequark
45d1dc1d54 vendor.board.tinyfpga_bx: fix typo. 2019-06-04 06:20:01 +00:00
whitequark
6426b90e4a vendor.conn.pmod: implement. 
Fixes #79.
 2019-06-03 16:49:59 +00:00
whitequark
0fa45b5e14 vendor.board: extract package. 2019-06-03 16:14:59 +00:00
whitequark
2ca0834d41 vendor.tinyfpga_bx: add connectors. 2019-06-03 15:40:57 +00:00
whitequark
7c5461d210 vendor.icestick: add connectors. 2019-06-03 15:15:45 +00:00
whitequark
f351e2bd1e vendor.ice40_hx1k_blink_evn: add (some) connectors. 
I have no idea how to lay out the Arduino-like connectors best,
so they're just missing.
 2019-06-03 15:03:49 +00:00
whitequark
ed64880cc4 build.{plat,res}: add support for connectors. 
Fixes #77.
 2019-06-03 15:02:15 +00:00
whitequark
639e64c388 vendor.fpga.lattice_ice40: implement differential output buffers. 2019-06-03 09:28:27 +00:00
whitequark
41adcc3f97 vendor.fpga.lattice_ice40: implement differential input buffers. 2019-06-03 08:38:12 +00:00
whitequark
3116d4add2 vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras. 2019-06-03 07:54:28 +00:00
whitequark
185abb492d vendor.fpga.lattice_ice40: implement SDR and DDR I/O buffers. 2019-06-03 07:43:31 +00:00
whitequark
6fae06aea9 build.{dsl,plat,res}: allow dir="oe". 
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
 2019-06-03 04:42:55 +00:00
whitequark
9ba2efd86b build.{res,plat}: use xdr=0 as default, not xdr=1. 
The previous behavior was semantically incorrect.
 2019-06-03 03:36:32 +00:00
whitequark
3327deae92 vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files. 2019-06-03 03:01:56 +00:00
whitequark
dc17d06fe9 vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras. 
The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
 2019-06-03 02:51:59 +00:00
whitequark
98497b2075 build.dsl: require a dict for extras instead of a stringly array. 
Fixes #72.
 2019-06-02 23:36:21 +00:00
whitequark
e4ebe03115 vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles. 2019-06-02 04:12:50 +00:00
whitequark
37152c733e vendor.tinyfpga_{b→bx} 2019-06-02 04:11:28 +00:00
whitequark
bff08c5016 vendor.tinyfpga_b: fix IO_STANDARD. 2019-06-02 04:04:07 +00:00
Simon Kirkby
358b98e5de vendor.tinyfpga_b: implement. 2019-06-02 01:20:09 +00:00
whitequark
39fad9a955 vendor.icestick: fix typo. 2019-06-02 01:13:03 +00:00
whitequark
ba0fcddb2c vendor.ice40_hx1k_blink_evn: implement. 2019-06-01 16:48:07 +00:00