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Author SHA1 Message Date
whitequark f22106e5ef back.rtlil: allow record slices on LHS. 2019-04-20 08:12:29 +00:00
whitequark 611c25f909 hdl.rec: fix slicing of records. 2019-04-19 19:55:39 +00:00
whitequark dda8f34d39 hdl.xfrm: handle classes that inherit from Record. 2019-04-18 17:06:33 +00:00
whitequark 287a0531b3 lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
whitequark 50fa2516fa hdl.ast: fix some type checks. 2019-04-10 04:33:44 +00:00
whitequark 0a2a7025a6 hdl.xfrm: allow using FragmentTransformer on any elaboratable. 
Fixes #29.
 2019-04-10 00:23:11 +00:00
whitequark 49eef77c53 hdl: remove deprecated get_fragment() and lower() methods. 2019-04-09 23:53:43 +00:00
whitequark a74cacdc69 hdl.ast: handle a common typo, such as Signal(1, True). 2019-04-03 14:59:01 +00:00
whitequark c9c9307a5e test_sim: add missing add_process(). 
Fixes #43.
 2019-03-28 17:50:14 +00:00
Luke Wren 23a07b955f lib.cdc: add optional reset to MultiReg, and document its use cases. 2019-03-28 05:21:48 +00:00
whitequark a57c72d606 back.rtlil: fix off-by-one in Part legalization. 
Fixes #52.
 2019-03-28 05:12:12 +00:00
anuejn 3c95299c4e hdl.rec: separate record and signal name with __, not _. 
This makes names of signals within records less ambiguous, in case
they themselves have underscores within them.
 2019-03-25 14:26:00 +00:00
whitequark 81ee2db163 hdl.ast: fix typo. 
Fixes #49.
 2019-03-25 10:50:39 +00:00
whitequark 4027317835 lib.fifo: register GrayEncoder output before CDC. 
Without this register, static hazards in the encoder could cause
multiple encoder output bits to toggle, which would be incorrectly
sampled by the 2FF synchronizer.

Reported by @Wren6991.
 2019-03-03 18:23:51 +00:00
whitequark e93bf4bf4b tracer: factor out get_var_name(default=). 2019-03-03 18:21:22 +00:00
whitequark cac4b10b82 hdl.rec: remove __slots__. 
Left in by mistake.
 2019-03-03 18:21:22 +00:00
whitequark 8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. 2019-02-14 20:52:42 +00:00
whitequark 43e4833ddb back.rtlil: accept ast.Const as cell parameter. 2019-01-26 23:25:54 +00:00
whitequark bc5a127fd2 hdl.ast: fix ValueKey for Cat. 2019-01-26 23:25:34 +00:00
whitequark e844b0e095 compat.fhdl.module: fix typo. 2019-01-26 23:08:55 +00:00
whitequark ce7ba70462 compat.fhdl.specials: fix __all__ list. 2019-01-26 22:59:33 +00:00
whitequark 6cd9f7db19 compat.genlib.resetsync: add shim for AsyncResetSynchronizer. 2019-01-26 18:24:36 +00:00
whitequark 2fb85a6170 compat.fifo: fix _FIFOInterface deprecation wrapper. 2019-01-26 18:23:58 +00:00
whitequark f44ca291c1 lib.cdc: add ResetSynchronizer. 2019-01-26 18:07:59 +00:00
whitequark e74dbc3377 back.pysim: support async reset. 2019-01-26 18:07:43 +00:00
whitequark 8686e9aa06 back.pysim: give better names to unnamed fragments and their signals. 
Was: top.#0, top.None_clk
Now: top.U0, top.U0_clk

(U for Unnamed, or similarly, an unit refdes.)
 2019-01-26 18:07:16 +00:00
whitequark b133eb735f back.rtlil: accept any elaboratable, not just fragments. 2019-01-26 16:11:29 +00:00
whitequark 4bf80a6e33 compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00
whitequark 7890c0adc8 test.compat: reenable tests converting to Verilog. 2019-01-26 15:29:09 +00:00
whitequark 4887771e4a compat.sim: fix deprecated stdlib import. 2019-01-26 15:26:54 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark 4922a73c5d test.compat: import tests from Migen as appropriate. 
test_signed and test_coding are adjusted slightly to account for
differences in comb propagation between the simulators; we might want
to revert that eventually.
 2019-01-26 01:01:03 +00:00
whitequark f71e0fffbb hdl.ast: fix shape calculation for *. 
This was carried over from Migen, and is wrong there too.
Counterexample: 1'sd-1 * 4'sd-4 = 4'sd-4 (but should be 5'sd4).
 2019-01-26 00:56:40 +00:00
whitequark 7b25665fde back.pysim: fix behavior of initial cycle for sync processes. 
The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.
 2019-01-25 20:37:56 +00:00
whitequark 1782b841b2 lib.fifo: in FIFOInterface.read(), check readable on the right cycle. 2019-01-22 07:03:46 +00:00
whitequark eeb023a7f5 compat.genlib.fifo: adjust _FIFOInterface shim to not require fwft=. 2019-01-22 06:56:46 +00:00
whitequark 2c80f35de4 lib.fifo: fix typo in AsyncFIFO documentation. 2019-01-22 05:47:50 +00:00
whitequark e33580cf4c lib.fifo: add AsyncFIFO and AsyncFIFOBuffered. 2019-01-21 16:02:46 +00:00
whitequark 12e04e4ee5 back.pysim: wake up processes before ever committing any values. 
Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
 2019-01-21 16:00:25 +00:00
whitequark 52a9f818f1 compat.genlib.cdc: add missing import. 2019-01-20 03:03:56 +00:00
whitequark c110fe6a9d compat.genlib.cdc: add GrayCounter and GrayDecoder shims. 2019-01-20 02:29:08 +00:00
whitequark b6cff2c098 lib.coding: add GrayEncoder and GrayDecoder. 
Unlike the Migen ones, these are purely combinatorial.
 2019-01-20 02:20:34 +00:00
whitequark 9757157fe2 lib.coding: add width as attribute to all coders. 2019-01-20 01:59:09 +00:00
whitequark 9de9272709 lib.fifo: use memory in the FIFO model. 
This is unfortunately more complicated, but results in a much faster
proof.
 2019-01-19 09:27:56 +00:00
whitequark 6ea0a12dd4 lib.fifo: use model equivalence to simplify formal specification. 
This is unfortunately slow, and should probably be using theory
of arrays.
 2019-01-19 09:27:56 +00:00
whitequark 38b3c4af31 hdl.ast: implement shape for modulo operator. 2019-01-19 09:27:56 +00:00
whitequark 5e2b46f727 hdl.ast: add Value.implies. 2019-01-19 08:56:44 +00:00
whitequark c5d67b0461 hdl.xfrm: mark internal registers used in lowering Sample(). 2019-01-19 07:27:32 +00:00
whitequark e3b5b2acc8 fhdl.specials: add compatibility shim for Tristate. 2019-01-19 02:20:40 +00:00
whitequark 3ed519383c lib.fifo: fix simulation read/write methods to take only one cycle. 2019-01-19 01:38:09 +00:00
whitequark 45088f7824 compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered. 2019-01-19 01:06:51 +00:00
whitequark 97b990272e lib.fifo: formally verify FIFO contract. 2019-01-19 00:52:56 +00:00
whitequark b50b47d984 hdl.ast: give Assert and Assume their own src_loc. 
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
 2019-01-19 00:08:51 +00:00
whitequark 66466a8a0e back.rtlil: only emit each AnyConst/AnySeq cell once. 
These are semantically like signals, not like constants.
 2019-01-18 01:34:48 +00:00
Alain Péteut 60089db075 cli: add missing default for generate 2019-01-17 20:45:07 +00:00
whitequark 5a831ce31c lib.fifo: add basic formal specification. 2019-01-17 05:40:25 +00:00
whitequark fa8e876356 hdl.ast: allow sampling ClockSignal, ResetSignal. 2019-01-17 05:23:06 +00:00
whitequark 8c96675580 hdl.ast: add Past, Stable, Rose, Fell. 2019-01-17 04:31:27 +00:00
whitequark 16f90d3585 formal: extract from toplevel module. 
The nMigen formal language is about to get *much* larger and will
keep growing faster than the rest of nMigen language, so it makes
good sense to extract it. Further, this makes it easier to qualify
formal keywords like `formal.AnyConst()` without directly importing
hdl.ast.
 2019-01-17 01:43:07 +00:00
whitequark 198efcad31 hdl.xfrm: add SampleLowerer. 2019-01-17 01:41:02 +00:00
whitequark b3de114d67 hdl.ast: add Sample. 2019-01-17 01:36:27 +00:00
whitequark b78a2be9f6 lib.fifo: port sync FIFO queues from Migen. 2019-01-16 17:20:38 +00:00
whitequark cb2f18ee37 hdl.ast: fix naming of Signal.like() signals when tracer fails. 2019-01-16 17:20:38 +00:00
whitequark f2425001aa back.rtlil: slightly nicer naming for $next signals. NFC. 2019-01-16 17:20:38 +00:00
whitequark 935bf2d8cf back.rtlil: rename \sig$next to $next$sig. 
These used to serve a useful purpose being public, back when the RTLIL
backend was immature. Not anymore; now they merely clutter up views
in gtkwave and so on.
 2019-01-16 14:51:20 +00:00
whitequark 6191760c30 Unbreak 655d02d5. 2019-01-15 23:09:10 +00:00
William D. Jones 655d02d5b8 back.rtlil: Generate $anyconst and $anyseq cells. 2019-01-15 22:52:45 +00:00
William D. Jones 77728c2dea hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children. 2019-01-15 22:52:45 +00:00
William D. Jones 6fdbc3d885 hdl.ast: Add AnyConst and AnySeq value types. 2019-01-15 22:52:45 +00:00
whitequark c4276f7cf7 lib.io: pass pin to platform.get_tristate(). 2019-01-14 21:39:19 +00:00
whitequark b534e92dd5 hdl.ir: allow explicitly requesting flattening. 2019-01-14 17:04:23 +00:00
whitequark 6f66885c09 lib.io: lower to platform-independent tristate buffer. 2019-01-14 16:50:04 +00:00
whitequark 011bf2258e hdl: make ClockSignal and ResetSignal usable on LHS. 
Fixes #8.
 2019-01-14 15:38:16 +00:00
whitequark 664b4bcb3a hdl.dsl: cases wider than switch test value are unreachable. 
In 3083c1d6 they were erroneously fixed via truncation.
 2019-01-13 08:51:49 +00:00
whitequark 3083c1d6dd hdl.dsl: accept (but warn on) cases wider than switch test value. 
Fixes #13.
 2019-01-13 08:46:28 +00:00
whitequark cbf7bd6e31 back.pysim: handle non-driven, non-port signals. 
Fixes #20.
 2019-01-13 08:31:38 +00:00
whitequark 06faeee357 back.verilog: better error message if Yosys is not found. 
Fixes #17.
 2019-01-13 08:10:23 +00:00
whitequark 307de722cb back.verilog: remove undriven check. 
This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.

Fixes #23.
 2019-01-08 22:43:09 +00:00
Adam Greig 560bb007cc Give the top level scope a name to fix VCD hierarchy. 2019-01-06 00:10:37 +00:00
whitequark a2b04d71d0 hdl.ast: allow slicing [n:n] into n-bit value. 2019-01-02 18:14:57 +00:00
whitequark ef1e0b8d55 back.rtlil: translate empty slices correctly. 2019-01-02 18:14:29 +00:00
William D. Jones f31055a4ef back.rtlil: Generate RTLIL for Assert/Assume statements. 2019-01-02 11:17:39 +00:00
William D. Jones f77dc40256 hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children. 2019-01-02 11:17:39 +00:00
William D. Jones 2412650f56 hdl.dsl: Support Assert and Assume where an Assign can occur. 2019-01-02 11:17:39 +00:00
William D. Jones e6517a33c7 hdl.ast: Add Assert and Assign statements. 2019-01-02 11:17:39 +00:00
whitequark ea7e19ed5c hdl.ast: experimentally add Value._as_const. 
Useful for writing e.g. decoders that accept Cat, etc as argument.
 2019-01-01 09:50:39 +00:00
whitequark 1a9dcd2f28 back.rtlil: fix typo. 2019-01-01 08:50:28 +00:00
whitequark 3c07d8d52c hdl.rec: include record name in error message. 2019-01-01 03:39:12 +00:00
whitequark 031a9e2616 hdl.rec: use a helpful error on unknown field reference. 2019-01-01 03:35:34 +00:00
whitequark d78e6c155b hdl.mem: add DummyPort, for testing and verification. 2019-01-01 03:08:10 +00:00
whitequark ae3c5834ed back.rtlil: match shape of Array elements to ArrayProxy shape. 
Fixes #15.
 2018-12-31 03:43:34 +00:00
whitequark cdc40eaa9b back.rtlil: fix typo. 2018-12-31 03:37:38 +00:00
whitequark 39eb2e8fa7 lib.cdc: fix tests to actually run. 2018-12-29 15:02:44 +00:00
whitequark 849c649259 back.pysim: warn if simulation is not run. 
This would have prevented 3ea35b85.
 2018-12-29 15:02:04 +00:00
whitequark 92a96e1644 hdl.rec: add basic record support. 2018-12-28 13:22:10 +00:00
whitequark d66bbb0df8 tracer: factor out get_src_loc(). 2018-12-28 01:31:24 +00:00
whitequark 3ea35b8566 lib.coding: fix tests to actually run, and fix code to fix tests. 2018-12-27 21:45:55 +00:00
whitequark 470d66934f hdl.dsl: add support for fsm.ongoing(). 2018-12-27 16:19:01 +00:00
whitequark de50ccec90 hdl.mem: add missing __all__. 2018-12-27 16:19:01 +00:00
Jean-François Nguyen 73ed870309 compat.genlib.coding: fix import. 2018-12-26 14:30:01 +00:00