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281 commits

Author SHA1 Message Date
whitequark 8730895d8c hdl.mem: allow changing init value after creating memory. 2018-12-22 01:09:03 +00:00
whitequark 6ee80408bb back.verilog: do not rename internal signals. 
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
 2018-12-22 00:53:40 +00:00
whitequark 5361b4c22b compat: fix confusing naming for memory port address signal. 2018-12-22 00:53:05 +00:00
whitequark f6772759c8 hdl.ir: fix port propagation between siblings, in the other direction. 2018-12-22 00:31:31 +00:00
whitequark 0df543b204 compat: do not finalize native submodules twice. 2018-12-22 00:02:31 +00:00
whitequark a4183eba69 hdl.mem: use more informative signal naming for ports. 2018-12-21 23:55:02 +00:00
whitequark 913339c04a hdl.ir: fix port propagation between siblings. 2018-12-21 23:53:18 +00:00
whitequark 00ef7a78d3 compat: provide verilog.convert shim. 2018-12-21 13:53:06 +00:00
whitequark fc7da1be2d hdl.ir: do not flatten instances or collect ports from their statements. 
This results in absurd behavior for memories.
 2018-12-21 13:52:18 +00:00
whitequark 568d3c5b7d compat: provide Memory shim. 2018-12-21 13:15:52 +00:00
whitequark fa2af27bb0 hdl.mem: ensure transparent read port model has correct latency. 2018-12-21 13:01:08 +00:00
whitequark 48d13e47ec back.pysim: handle out of bounds ArrayProxy indexes. 2018-12-21 12:32:08 +00:00
whitequark 7ae7683fed back.pysim: give numeric names to unnamed subfragments in VCD. 2018-12-21 12:29:33 +00:00
whitequark af7db882c0 hdl.mem: use different naming for array signals. 
It looks like [] is confusing gtkwave somehow.
 2018-12-21 12:26:49 +00:00
whitequark e58d9ec74d hdl.mem: add simulation model for memory. 2018-12-21 11:54:32 +00:00
whitequark a40e2cac4b back.pysim: fix an issue with too few funclet slots. 2018-12-21 10:25:28 +00:00
whitequark c49211c76a hdl.mem: add tests for all error conditions. 2018-12-21 06:07:16 +00:00
whitequark a061bfaa6c hdl.mem: tie rdport.en high for asynchronous or transparent ports. 2018-12-21 04:22:16 +00:00
whitequark 8d58cbf230 back.rtlil: more consistent prefixing for subfragment port wires. 2018-12-21 04:21:11 +00:00
whitequark b0bd7bfaca hdl.ir: correctly handle named output and inout ports. 2018-12-21 04:03:03 +00:00
whitequark 2b4a8510ca back.rtlil: implement memories. 2018-12-21 01:55:59 +00:00
whitequark 6d9a6b5d84 hdl.mem: implement memories. 2018-12-21 01:53:32 +00:00
whitequark 6672ab2e3f back.rtlil: explicitly pad constants with zeroes. 
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
 2018-12-21 01:51:18 +00:00
whitequark 221f108fbe back.rtlil: fix translation of Cat. 2018-12-21 01:48:02 +00:00
whitequark f7fec804ec ir: allow non-Signals in Instance ports. 2018-12-20 23:40:40 +00:00
whitequark 0f2c7e7161 compat: import genlib.record from Migen. 2018-12-18 20:04:22 +00:00
whitequark a90748303c compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices. 2018-12-18 20:03:32 +00:00
whitequark dbbcc49a71 hdl.ast: Cat.{operands→parts} 2018-12-18 19:15:50 +00:00
whitequark 4199674edd back.pysim: implement *. 2018-12-18 18:02:21 +00:00
whitequark 07e9cfa939 test.sim: add tests for sync functionality and errors. 2018-12-18 17:53:50 +00:00
whitequark 7fa82a70be back.pysim: eliminate most dictionary lookups. 
This makes the Glasgow testsuite about 30% faster.
 2018-12-18 16:36:54 +00:00
whitequark 7341d0d7ef hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim. 2018-12-18 16:13:29 +00:00
whitequark c5f169988b back.pysim: use arrays instead of dicts for signal values. 
This makes the Glasgow testsuite about 40% faster.
 2018-12-18 05:20:20 +00:00
whitequark 39605ef551 back.pysim: naming. NFC. 2018-12-18 04:46:36 +00:00
whitequark 65702719e8 back.pysim: fix an off-by-1 in add_sync_process(). 2018-12-18 04:43:04 +00:00
whitequark 34b81d0b87 back.pysim: trigger processes waiting on Tick() exactly at clock edge. 2018-12-18 04:37:39 +00:00
whitequark d6e98fd934 back.pysim: continue running simulator processes until they suspend. 2018-12-18 03:05:16 +00:00
whitequark c7f9386eab fhdl.ir: add black-box fragments, fragment parameters, and Instance. 2018-12-17 22:55:39 +00:00
whitequark 8d1639a5a8 hdl, back: add and use SignalSet/SignalDict. 2018-12-17 17:21:29 +00:00
whitequark 8c4de99c0d hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC. 2018-12-17 17:21:29 +00:00
whitequark f1e390cbc9 back.rtlil: update for Yosys master. 2018-12-17 15:50:43 +00:00
whitequark 850674637a back.rtlil: implement Array. 2018-12-17 01:15:23 +00:00
whitequark 87cd045ac3 back.rtlil: implement Part. 2018-12-17 01:05:08 +00:00
whitequark f968678937 back.rtlil: handle reset_less domains. 2018-12-16 23:52:47 +00:00
whitequark 015998eba9 hdl.dsl: add clock domain support. 2018-12-16 23:51:24 +00:00
whitequark b2f828387a hdl.dsl: cleanup. NFC. 2018-12-16 23:44:00 +00:00
whitequark 91b7561a00 back.rtlil: extract _StatementCompiler. NFC. 2018-12-16 22:26:58 +00:00
whitequark b9a0af8bde back.rtlil: simplify. NFC. 2018-12-16 21:00:00 +00:00
whitequark 635094350f back.rtlil: properly escape strings in attributes. 2018-12-16 20:27:36 +00:00
whitequark 33f32a25f5 back.rtlil: prepare for Yosys sigspec slicing improvements. 
See YosysHQ/yosys#741.
 2018-12-16 18:03:14 +00:00
whitequark db5fd1e4c4 compat.fhdl.structure: only convert to bool in If/Elif if necessary. 2018-12-16 17:41:42 +00:00
whitequark 9bce35098f back.rtlil: avoid illegal slices. 
Not sure what to do with {} [] on LHS yet--fix Yosys?
 2018-12-16 17:41:11 +00:00
whitequark e86104d3a6 back.rtlil: use slicing to match shape when reducing width. 2018-12-16 16:20:45 +00:00
whitequark 2833b36c73 back.rtlil: don't emit a slice if all bits are used. 2018-12-16 16:05:38 +00:00
whitequark 9794e732e2 back.rtlil: reorganize value compiler into LHS/RHS. 
This also implements Cat on LHS.
 2018-12-16 13:33:34 +00:00
whitequark ed39748889 back.rtlil: fix naming. NFC. 2018-12-16 11:26:31 +00:00
whitequark 2be76fda3c hdl.xfrm: separate AST traversal from AST identity mapping. 
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
 2018-12-16 11:25:52 +00:00
whitequark 286a8009c8 compat.fhdl: reexport Array. 2018-12-16 10:39:54 +00:00
whitequark d4e8d3e95a back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. 2018-12-16 10:31:42 +00:00
whitequark d9579219ee test.sim: generalize assertOperator. NFC. 2018-12-15 21:08:29 +00:00
whitequark bdb8db2826 back.pysim: add (stub) LHSValueCompiler. 2018-12-15 21:01:38 +00:00
whitequark 20a04bca88 back.pysim: implement Part. 2018-12-15 20:58:06 +00:00
whitequark 54fb999c99 back.pysim: implement ArrayProxy. 2018-12-15 19:37:36 +00:00
whitequark 80c5343600 hdl.ast: implement Array and ArrayProxy. 2018-12-15 17:16:31 +00:00
whitequark c6e7a93717 hdl: appropriately rename tests. NFC. 2018-12-15 16:13:53 +00:00
whitequark f603b735e8 hdl.ast: improve ClockSignal, ResetSignal documentation. 2018-12-15 14:58:31 +00:00
whitequark 790eb05a92 Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
whitequark b5a1efa0c8 Move star imports to make from nmigen import * usable. 2018-12-15 14:20:10 +00:00
whitequark 1f10bd96b9 Determine Migen's API surface and document compatibility summary. 
This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.
 2018-12-15 11:52:30 +00:00
whitequark b70340c0da pyback.sim: test Slice, Cat, Repl. 2018-12-15 10:09:14 +00:00
whitequark db4600d52b fhdl.ast, back.pysim: implement shifts. 2018-12-15 09:58:30 +00:00
whitequark 46f5addf05 fhdl.ast: refactor Operator.shape(). NFC. 2018-12-15 09:46:20 +00:00
whitequark 3a8685c352 Consistently use '{!r}' in and only in TypeError messages. 2018-12-15 09:31:58 +00:00
whitequark f9f7921959 fhdl.ir: test iter_comb(), iter_sync() and iter_signals(). 2018-12-15 09:26:36 +00:00
whitequark f5e8c9033d fhdl.ir: fix incorrect uses of positive to say non-negative. 
Also test Part and Slice properly.
 2018-12-15 09:26:23 +00:00
whitequark 9010805040 compat.fhdl.structure: handle If/Elif with multi-bit condition. 2018-12-15 00:10:54 +00:00
whitequark ecea721f43 compat.fhdl.module: allow adding native submodules to compat modules. 2018-12-14 23:56:50 +00:00
whitequark 1c7b43ea49 Fix deprecations in Python 3.7. 2018-12-14 23:56:50 +00:00
whitequark 7108111ad0 back.pysim: preserve process locations through add_sync_process(). 2018-12-14 23:27:36 +00:00
whitequark c4ba5a3915 fhdl.ast: clean up stub error messages. NFC. 2018-12-14 23:07:16 +00:00
whitequark 2001359b66 fhdl.ir: automatically flatten hierarchy to resolve driver conflicts. 
Fixes #5.
 2018-12-14 22:48:17 +00:00
whitequark 579feaba4e fhdl.ir: Fragment.{drive→add_driver} 2018-12-14 20:58:29 +00:00
whitequark 0015713bfb back.pysim: count delta cycles separately to avoid clock drift. 2018-12-14 20:52:41 +00:00
whitequark a6a8703a0e back.pysim: simplify. 2018-12-14 20:45:45 +00:00
whitequark 7e3cf26cf8 back.pysim: revert 70ebc6f2. 2018-12-14 19:46:08 +00:00
whitequark 71304c9fe7 back.pysim: fix implicit boolean conversion. 2018-12-14 19:08:06 +00:00
whitequark fe5fb34fae back.pysim: squash one level of hierarchy. 
There's really no point in the "top" node.
 2018-12-14 18:53:21 +00:00
whitequark 70ebc6f2c1 back.pysim: implement blocking assignment semantics correctly. 2018-12-14 18:47:12 +00:00
whitequark 120d817123 back.pysim: undriven sync signals should return to previous value. 2018-12-14 17:25:48 +00:00
whitequark 4f5b4a9bf4 back.pysim: in simulator sync processes, start by waiting for a tick. 
This matches Migen behavior and also makes more sense.
 2018-12-14 17:05:11 +00:00
whitequark e230383aac back.pysim: make initial phase configurable. 2018-12-14 16:46:16 +00:00
whitequark 0ef5ced492 compat.sim: match clock period. 2018-12-14 16:39:52 +00:00
whitequark 17d26c8329 compat: add run_simulation shim. 2018-12-14 16:22:18 +00:00
whitequark 88970ee29f pysim.back: fix add_sync_process wrapper to handle signals correctly. 2018-12-14 16:21:53 +00:00
whitequark 3bc3647380 compat.fhdl.module: fix specials. 2018-12-14 16:14:08 +00:00
whitequark 3b23645fb7 compat: add fhdl.specials.TSTriple shim. 2018-12-14 16:09:51 +00:00
whitequark 7200346249 genlib.io: import TSTriple from Migen. 2018-12-14 16:09:51 +00:00
whitequark 50ba443f92 fhdl.ast: fix Switch with constant test. 2018-12-14 16:09:51 +00:00
whitequark a0d555a9fc compat: add genlib.cdc.MultiReg shim. 2018-12-14 16:01:38 +00:00
whitequark baba47251c compat.fhdl.module: update deprecation messages. 2018-12-14 16:01:38 +00:00
whitequark 9307a31678 back.pysim: Simulator({gtkw_signals→traces}=). 2018-12-14 15:23:22 +00:00
whitequark e3f32a1faf back.pysim: better naming. NFC. 2018-12-14 15:21:13 +00:00
whitequark 474d46ced8 back.pysim: implement most operators and add tests. 2018-12-14 14:21:22 +00:00
whitequark d9aaf0114b back.pysim: close .vcd/.gtkw files on context manager exit. 2018-12-14 13:59:03 +00:00
whitequark 1655b59d1b back.pysim: show more legible names for processes in errors. 2018-12-14 13:50:19 +00:00
whitequark 625c55a3b8 back.pysim: throw exceptions back at processes. 2018-12-14 13:43:25 +00:00
whitequark 654722ce14 back.pysim: add gtkw traces even more robustly. 2018-12-14 13:43:08 +00:00
whitequark 7d3f7f277a back.pysim: accept (and evaluate) generator functions. 2018-12-14 13:32:30 +00:00
whitequark 7fc9f98b98 back.pysim: skip VCD signal population if VCD is not requested. 2018-12-14 13:32:30 +00:00
whitequark 3ad79ec690 back.pysim: allow processes to evaluate expressions. 2018-12-14 13:32:30 +00:00
whitequark 151d079f01 fhdl.ir: oops, we defined DomainError twice. 2018-12-14 12:59:54 +00:00
whitequark dd00b5e2d6 back.pysim: more general clean-up. 2018-12-14 12:46:04 +00:00
whitequark 1b7f8c7950 back.pysim: general clean-up. 2018-12-14 12:22:03 +00:00
whitequark 105113f1d8 back.pysim: accept any valid assignments from processes. 2018-12-14 12:18:41 +00:00
whitequark 240a40c2c2 back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw. 2018-12-14 10:57:13 +00:00
whitequark 7d91dd56c8 fhdl.xfrm: implement DomainLowerer. 2018-12-14 10:56:53 +00:00
whitequark b34c1a9ad0 back.pysim: undriven comb signals should return to reset value. 2018-12-14 09:12:38 +00:00
whitequark b58715c5dc ast, back.pysim: allow specifying user-defined decoders for signals. 2018-12-14 09:02:29 +00:00
whitequark bb843cb40c back.pysim: fix completely broken codegen for Switch. 2018-12-14 08:51:36 +00:00
whitequark 6aefd0c04c back.pysim: raise an exception if delta cycles blow a process deadline. 2018-12-14 08:10:21 +00:00
whitequark a10791e160 back.pysim: if requested, write a gtkw file with a useful preset. 2018-12-14 08:04:29 +00:00
whitequark cb998d891b back.pysim: explain how delta cycles work. 2018-12-14 07:26:26 +00:00
whitequark e4d08d2855 back.pysim: delay clock processes by one half period. 
Makes it easier to see initial delta cycles.
 2018-12-14 05:17:43 +00:00
whitequark 3bb7a87e0f back.pysim: implement "sync processes", like migen.sim generators. 2018-12-14 05:13:58 +00:00
whitequark d791b77cc8 back.pysim: allow suspending processes until a tick in a domain. 2018-12-14 04:33:06 +00:00
whitequark 3e59d857e1 back.pysim: use bare ints for signal values (-5% runtime). 2018-12-14 03:05:57 +00:00
whitequark b09f4b10ee back.pysim: collect handlers before running (-5% runtime). 2018-12-13 18:34:44 +00:00
whitequark a7ebc02bdd back.pysim: allow multiple registered handlers per signal. 2018-12-13 18:28:11 +00:00
whitequark 6a4004ef8d back.pysim: fix handling of process termination. 2018-12-13 18:17:58 +00:00
whitequark fb27c2520b back.pysim: new simulator backend (WIP). 2018-12-13 18:02:46 +00:00
whitequark 71f1f717c4 fhdl.cd: rename ClockDomain signals together with domain. 2018-12-13 15:24:55 +00:00
whitequark 07c818e077 fhdl.ir: move Fragment prepare logic from back.rtlil. 2018-12-13 14:34:07 +00:00
whitequark ac498414ab back.verilog: remove debug code. 2018-12-13 13:42:54 +00:00
whitequark 90f1503c91 fhdl.ir: record port direction explicitly. 
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
 2018-12-13 13:12:31 +00:00
whitequark 6251c95d4e compat.genlib.fsm: import/wrap Migen code. 2018-12-13 12:41:19 +00:00
whitequark 9661e897e6 fhdl.ir: a subfragment's input that we don't drive is also our input. 2018-12-13 11:50:56 +00:00
whitequark bb04c9e0da fhdl, back: trace and emit source locations of values. 2018-12-13 11:44:06 +00:00
whitequark 859c2dbcf0 back.rtlil: never give subfragment cells names starting with $. 2018-12-13 11:30:16 +00:00
whitequark b150f1915d fhdl.ir: don't crash propagataing ports in empty fragments. 2018-12-13 11:25:49 +00:00
whitequark 72257b6935 fhdl.ir: implement clock domain propagation. 2018-12-13 11:01:03 +00:00
whitequark fde2471963 fhdl.ir: remove iter_domains(). 2018-12-13 10:18:57 +00:00
whitequark f4340c19bb fhdl: cd_name→domain. 2018-12-13 10:15:01 +00:00
whitequark c5087edfa5 fhdl.cd: add tests. 2018-12-13 09:19:16 +00:00
whitequark 9bee90f1bd fhdl.xfrm: implement DomainRenamer. 2018-12-13 08:57:14 +00:00
whitequark 8963ab5d9f fhdl.xfrm: add test for ControlInserter with subfragments. 2018-12-13 08:45:10 +00:00
whitequark 19aa404628 fhdl.xfrm: add tests for ResetInserter, CEInserter. 2018-12-13 08:39:02 +00:00
whitequark b1a89ef5fd fhdl.ir: add tests for port propagation. 2018-12-13 08:09:39 +00:00
whitequark a797e27573 fhdl.dsl: add tests for lowering. 99% branch coverage. 2018-12-13 07:33:59 +00:00
whitequark d2e2d00e45 fhdl.cd: rename ClockDomain.{reset→rst}. 2018-12-13 07:27:27 +00:00
whitequark e0a81edf4d fhdl.dsl: add tests for submodules. 2018-12-13 07:24:28 +00:00