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Author SHA1 Message Date
Wanda 890e099ec3 Implement RFC 45: Move hdl.Memory to lib.Memory. 2024-02-19 22:24:58 +00:00
Wanda 6d65dc1366 hdl, back.rtlil: track and emit module/submodule locations. 2024-02-19 21:41:32 +00:00
Wanda 6058ad35cf hdl._ast: make Shape immutable and hashable. 
Fixes #1127.
 2024-02-16 15:21:05 +00:00
Wanda 24a392887a Implement RFC 43: Rename reset= to init=. 2024-02-15 22:52:24 +00:00
Wanda e3324e1456 hdl._dsl: fix using 0-width Switch with integer keys. 
Fixes #1133.
 2024-02-14 19:13:14 +00:00
Wanda 5ffb48b5fb hdl._ast: fix using 0-width Switch with integer keys. 
This comes up in `AssignmentLegalizer`-produced `Switch`es for
`ArrayProxy`.
 2024-02-14 11:52:35 +00:00
Wanda 0ecd06a7e5 sim: fix using 0-width Switch. 2024-02-14 11:51:19 +00:00
Wanda 0da439cce1 hdl._ast: deprecate ValueCastable.lowermethod. 2024-02-13 05:06:06 +00:00
Wanda e2fd819742 hdl._ast: fix shift_right and as_signed edge cases. 2024-02-13 04:52:38 +00:00
Catherine 0056e982c5 docs/reference: document Value, ValueCastable, ValueLike. 
Co-authored-by: Wanda <wanda@phinode.net>
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
 2024-02-13 03:22:04 +00:00
Wanda 4014f6429c Implement RFC 27 amendment: deprecate add_sync_process, not add_process. 2024-02-12 18:26:48 +00:00
Wanda 2d42d649ee tests: stop using implicit ports. 2024-02-12 13:24:54 +00:00
Catherine 6f44438e58 hdl._ir,hdl._nir,back.rtlil: new intermediate representation. 
The new intermediate representation will enable global analyses
on Amaranth code without lowering it to another representation
such as RTLIL.

This commit also changes the RTLIL builder to use the new IR.

Co-authored-by: Wanda <wanda@phinode.net>
 2024-02-11 09:03:49 +00:00
Catherine 78981232d9 hdl.xfrm: add assignment legalizer. 
Co-authored-by: Wanda <wanda@phinode.net>
 2024-02-11 09:03:49 +00:00
Wanda 45dbce13df hdl: consistently use "comb" for combinatorial domain. 
Fixes #1097.
 2024-02-09 19:32:55 +00:00
Wanda b6c5294e50 hdl.MemoryInstance: refactor and add first-class simulation support. 2024-02-09 17:36:15 +00:00
Wanda f4daf74634 sim: Add tests for memory access. 2024-02-09 17:36:15 +00:00
Wanda 6e06fc013f hdl.ir: associate statements with domains. 
Fixes #1079.
 2024-02-09 05:33:16 +00:00
Wanda 09854fa775 hdl.ast: make it impossible to construct *Castable instances. 
Fixes #1072.
 2024-02-09 05:26:58 +00:00
Catherine 9e75962c35 Implement RFC 27: Testbench processes for the simulator. 
Co-authored-by: Wanda <wanda@phinode.net>
 2024-02-06 23:12:07 +00:00
Wanda f48b8650c4 sim: fix simulation loop when process catches an injected exception. 2024-02-06 18:55:11 +00:00
Vegard Storheil Eriksen 5e2f3b7992 Implement RFC 42: Const from shape-castable. 2024-02-06 10:18:12 +00:00
Wanda 089213e19f Implement RFC 46: Change Shape.cast(range(1)) to unsigned(0). 2024-02-06 10:05:10 +00:00
Catherine 357ffb680c hdl: remove Repl per RFC 10. 
Closes #770.
 2024-01-31 03:01:35 +00:00
Catherine ea3d6c9557 docs/reference: document compat guarantee, importing, shapes. 
This commit also contains a related semantic change: it adds `Shape`
and `ShapeCastable` to the `__all__` list in `amaranth.hdl`. This is
consistent with the policy that is laid out in the new documentation,
which permits such additions without notice.

Co-authored-by: mcclure <mcclure@users.noreply.github.com>
 2024-01-30 22:54:18 +00:00
Catherine 5dd1223cf8 amaranth.hdl: start all private names with an underscore. 
This change completes commit 9dc0617e and makes all the tests pass.
It corresponds with the ongoing langauge reference documentation effort.

Fixes #781.
 2024-01-30 17:20:45 +00:00
Catherine 8678d5fa14 hdl.dsl: warn if a case is defined after a default case. 2024-01-30 02:54:48 +00:00
Wanda e9299ccd0e hdl.ast: change warning on out-of-range reset to an error, improve it. 
Fixes #1019.
 2024-01-30 02:35:26 +00:00
Wanda b40c18fb00 hdl.ast: suggest bit_select or word_select when indexing with Value. 
Fixes #1044.
 2024-01-18 20:06:55 +00:00
Wanda ae36b596bb hdl.mem: Switch to first-class IR representation for memories. 
Fixes #611.
 2024-01-17 08:10:28 +00:00
Wanda bf8faea51e hdl.ast: raise a sensible error for xxx in Value 2024-01-14 00:36:44 +00:00
Wanda 86d14f584e Implement RFC 39: Change semantics of no-argument m.Case(). 2024-01-13 22:33:54 +00:00
Wanda 7f76914b74 Implement RFC 17: Remove log2_int. 
Reexports of `amaranth.utils` functions are removed from
`amaranth._utils` to avoid a circular import issue (for `deprecated`).
Since this is a private module, this should not be a problem.
 2024-01-11 04:45:17 +00:00
Wanda ea258fad71 Change uses of Case() to Default() in preparation for RFC 39. 2024-01-11 04:44:02 +00:00
Jaro Habiger ded84fe9d6 sim: fix ValueCastable not being recognized as a coroutine command 2024-01-05 14:30:38 +00:00
Jaro Habiger cc9fe89049 hdl.ast: fix Array not being indexable by ValueCastable 2024-01-03 13:46:16 +00:00
Wanda 0849e1af0b hdl.ast: make Slice const-castable. 
Fixes #1006.
 2023-12-30 11:28:03 +00:00
Wanda 6780c838b2 hdl.ast: fix Const.cast(Cat(...)) handling for signed numbers. 2023-12-30 11:27:08 +00:00
Wanda 8cd8cdde2b Implement RFC 20: Remove non-FWFT FIFOs. 
Fixes #875.
 2023-12-13 11:41:19 +00:00
Catherine 9d4ffab104 compat: remove. 
Fixes #692.
 2023-12-13 11:20:12 +00:00
Catherine 750cbbc3c7 hdl: remove deprecated Sample, Past, Stable, Rose, Fell. 2023-12-13 11:13:14 +00:00
Catherine 475b0f35dd Implement RFC 19: Remove amaranth.lib.scheduler. 
Closes #874.
 2023-12-13 09:53:54 +00:00
Catherine a2aa07cbc7 lib.wiring: document amaranth-lang/rfcs#2. WIP 
Co-authored-by: Charlotte <charlotte@hrzn.ee>
 2023-12-11 22:57:30 +00:00
Jean-François Nguyen d154bddf17 lib.wiring: preserve insertion order in SignatureMembers.__iter__. 2023-12-11 22:34:57 +00:00
Wanda 8e6ae9e6e0 Implement RFC 38: Component signature immutability. 
Fixes #996.
 2023-12-11 19:51:32 +00:00
Wanda 6ad0d21cc9 Implement RFC 37: Make `Signature` immutable. 
Fixes #995.
 2023-12-11 19:01:32 +00:00
Catherine b9c2404f22 lib.wiring: make values of In and Out be strings "In" and "Out". 
Their `str()` and `repr()` values are already that; and the 0 and 1
don't make sense. The RFC leaves it unspecified.
 2023-12-11 18:04:37 +00:00
Wanda e9545efb22 Implement RFC 35: Add ShapeLike, ValueLike. 2023-12-09 13:57:30 +00:00
Wanda 422ba9ea51 lib.wiring: use tracer to obtain default Signature path and src_loc. 
Fixes #987.
 2023-12-07 21:50:34 +00:00
Catherine 120375dabe lib.wiring: fix __repr__ for PureInterface subclasses. 
Fixes #988.
 2023-12-05 04:46:11 +00:00
Wanda 0cdcab0fbb Implement RFC 34: Rename amaranth.lib.wiring.Interface to PureInterface. 2023-12-04 21:41:47 +00:00
Wanda ab6503e352 lib.wiring: add __repr__ to Interface. 2023-12-03 02:00:20 +00:00
Wanda ef5cfa72bc Implement RFC 31: Enumeration type safety. 2023-11-29 10:50:34 +00:00
Wanda c6000b1097 lib.data: implement equality for View, reject all other operators. 2023-11-27 21:44:52 +00:00
Catherine 04f906965a lib.wiring: in is_compliant(sig, obj), check that obj is an interface object with that signature. 
Fixes #935.
 2023-11-27 18:50:41 +00:00
Catherine 8b48af6de8 lib.wiring: make sig.members += actually work. 2023-11-27 15:42:24 +00:00
Catherine a2e87b370e lib.wiring: fix typo in Signature.flatten. 2023-11-27 15:42:24 +00:00
Wanda 57748a66a6 lib.io: fix Pin.eq to work when FlippedInterface is involved. 
This was broken by #915, when platform started handing out
`FlippedInterface` versions of `Pin`.
 2023-11-27 06:35:55 +00:00
Catherine 74e613b49d lib.wiring: expand flipped object forwarding to respect @property and del. 
Although `@property` is the most common case, any descriptors are now
properly supported.

The special casing of methods goes away as they work by having functions
implement the descriptor protocol. (`__get__` has some special behavior
to make this possible.)

This is some of the most cursed code I have ever written, yet it is
obviously necessary.
 2023-11-26 12:53:59 +00:00
Catherine 79adbed313 sim.pysim: move name extractor functionality to Fragment. 
At the moment there are two issues with assignment of names in pysim:
1. Names are not deduplicated. It is possible (and frequent) for names
   to be included twice in VCD output.
2. Names are different compared to what is emitted in RTLIL, Verilog,
   or CXXRTL output.

This commit fixes issue (1), and issue (2) will be fixed by the new IR.
 2023-11-25 06:26:36 +00:00
Catherine 28e1d2833f test_lib_fifo: eliminate uses of deprecated Past and Rose. 2023-11-25 01:22:32 +00:00
William D. Jones abd74ead55 lib.wiring: flip sub-interfaces accessed via FlippedInterface. 2023-11-22 03:07:41 +00:00
Catherine f9da3c0d16 Pyupgrade to 3.8+. NFCI 2023-11-14 13:07:21 +00:00
Vegard Storheil Eriksen 879601380d ast: allow overriding Value operators. 2023-10-30 20:17:51 +00:00
Wanda 1c3227d956 lib.enum: use plain EnumMeta as metaclass when shape not used. 2023-10-25 17:00:24 +00:00
Wanda 4e4085a95b Implement RFC 20: Deprecate non-FWFT FIFOs. 
Tracking issue #875.
 2023-10-24 20:49:51 +00:00
Wanda a60b9960c5 lib.fifo: reimplement SyncFIFOBuffered without inner SyncFIFO. 2023-10-24 20:49:51 +00:00
Wanda e53d78474f test_lib_wiring: squash UnusedElaboratable warnings. 2023-10-24 20:18:16 +00:00
Wanda 00699f7c41 lib.enum: allow using functional syntax for enum creation. 
Fixes #910.
 2023-10-21 05:46:12 +00:00
Vegard Storheil Eriksen 392ead8d00 lib.data: return View from .const() 2023-10-10 09:59:37 +00:00
Wanda 470477a88f lib.wiring: fix Component.signature on subclasses without annotations. 
On Python <3.10, classes without annotations do not get an
`__annotations__` member at all, so the `getattr` on a subclass falls
back to the parent class `__annotations__`, attempting to create
signature members twice.  Fix that by looking at the `__dict__` instead.
 2023-10-08 22:49:47 +00:00
Wanda ccf7aaf00d sim._pyrtl: fix masking for bitwise operands and muxes. 
Fixes #926.
 2023-10-05 12:26:47 +00:00
Wanda c9416674d1 hdl.mem: fix transparent read handling for simple write ports. 
Fixes #922.
 2023-10-03 09:39:32 +00:00
Catherine a90bc7b91a lib.wiring: create flipped interface from flipped signature. 
Fixes #914.

Co-authored-by: Nelson Gauthier <nelson.gauthier@gmail.com>
 2023-09-27 11:17:29 +00:00
Wanda 05cb82b8fc ast: fix const-castable expression handling in Signal(reset=). 
The code to accept const-castable expressions was previously added in
0c4fda92fe, but it was untested and had
a few bugs.

Fixes #911.
 2023-09-24 02:46:43 +00:00
Catherine 4e078322a0 lib.io: make Pin an interface object. 
Tracking #879.

The directions of signals in `Pin` make it convenient to use a pin
signature in a component, such as in:

    class LEDDriver(Component):
        pins: Out(Signature({"o": Out(1)}))

    led_driver = LEDDriver()
    connect(led_driver.pins, platform.request("led"))

The `platform.request` call, correspondingly, returns a flipped `Pin`
object.
 2023-09-04 20:48:36 +00:00
Catherine 87fbcedecf lib.wiring: implement Signature.flatten. 2023-09-04 19:05:49 +00:00
Catherine f135226a79 hdl: disallow signed(0) values with unclear semantics. 
Fixes #807.
 2023-09-03 04:37:59 +00:00
Catherine 21b5451036 ast: ensure Part offset is unsigned. 
Co-authored-by: Marcelina Kościelnicka <mwk@0x04.net>
 2023-09-03 04:25:08 +00:00
Marcelina Kościelnicka 8c4a15ab92 hdl.mem: lower Memory directly to $mem_v2 RTLIL cell. 
The design decision of using split memory ports in the internal
representation (copied from Yosys) was misguided and caused no end
of misery. Remove any uses of `$memrd`/`$memwr` and lower memories
directly to a combined memory cell, currently the RTLIL one.
 2023-09-03 03:27:51 +00:00
Catherine f28b20fc84 lib.wiring: ensure flipped(flipped(intf)) is intf. 2023-09-01 05:42:04 +00:00
Catherine 5a17f94fdc hdl.rec: deprecate in favor of lib.data and lib.wiring. 
Tracking #879.
 2023-09-01 04:20:16 +00:00
Catherine cd4ea96bd1 Implement RFC 19: Remove amaranth.lib.scheduler 2023-09-01 00:56:12 +00:00
Catherine 44d5fac01c lib.wiring: fix equality of FlippedSignature with other object. 
Fixes #882.
 2023-08-31 19:26:07 +00:00
Catherine f95fe45186 Implement RFC 22: Add ValueCastable.shape(). 
Fixes #794.
Closes #876.
 2023-08-23 10:48:48 +00:00
Catherine 4ffadff20d lib.wiring: implement amaranth-lang/rfcs#2. 
Co-authored-by: Charlotte <charlotte@lottia.net>
 2023-08-22 16:22:09 +00:00
Marcelina Kościelnicka f6c38061ff lib.data: fix Layout.const masking for signed fields. 
Fixes #846.
 2023-07-22 00:35:42 +00:00
Catherine d1ca9c46a5 lib.data: allow Const as value of Layout.const(...) field. 
Fixes #838.
 2023-07-18 14:35:57 +00:00
Catherine 385b10d743 lib.data: improve diagnostics for field access on array layout view. 
Fixes #837.
 2023-07-18 14:35:49 +00:00
Charlotte 7e438180e0 lib.enum: allow empty enums. 2023-07-04 10:28:22 +00:00
Adam Greig 45b9730786 Implement RFC 6: CRC Generator 
See amaranth-lang/rfcs#6 and #681.
 2023-06-29 02:42:47 +00:00
Charlotte fd4e25df42 test_sim: failing test case. 2023-06-29 01:28:44 +00:00
Catherine b77e33f16a Drop support for Python 3.7. 2023-06-28 14:50:30 +00:00
Charlotte 59a83cf7eb test_sim: add failing test case for bitwise binary ops. 
See https://github.com/amaranth-lang/amaranth/pull/826#event-9609577585.
 2023-06-24 06:34:48 +00:00
Charlotte 4ec9cbbffe sim._pyrtl: py3.12+: convert to int before bitwise negating. 
Amaranth bitwise negation `~` compiles to Python bitwise negation `~` in
simulation; the same holds for comparison operators such as `==`. Thus
an expression such as `~(a == b)` in simulation will compile to Python
that takes the bitwise negation of the comparison result, which will be
an actual bool.

On 3.12, the result is a `DeprecationWarning` emitted only at simulation
run-time.

When negating in simulation, coerce the value to an int. `mask` is
sufficient as we do no further arithmetic here.
 2023-06-22 17:37:30 +00:00
Charlotte 63f9976267 tests.test_sim.SimulatorRegressionTestCase.test_bug_588: fix for Windows paths. 2023-06-22 03:52:55 +00:00
Charlotte d218273b9b hdl.ast: deprecate Repl and remove from AST; add Value.replicate. 2023-06-22 03:52:55 +00:00
Marcelina Kościelnicka b1cce87630 hdl.ast: make Value.__abs__ return unsigned shape. 2023-06-07 23:20:26 +00:00
Marcelina Kościelnicka 1d5e090580 hdl.ast: fix shape for subtraction. 
Fixes #813.
 2023-06-07 12:34:30 +00:00
Marcelina Kościelnicka 3180a17fd9 hdl.ast: fix Slice validation. 
Fixes #810.
 2023-06-07 12:26:36 +00:00
Marcelina Kościelnicka c7984463c7 hdl.ast: fix range handling in Shape.cast. 
Fixes #803.
 2023-06-07 12:26:30 +00:00
Marcelina Kościelnicka a6e33abc5f hdl.ast: guard rotate_* against 0-width values. 
Fixes #808.
 2023-06-07 12:12:24 +01:00
Marcelina Kościelnicka 656db317d2 hdl.ast: fix signed Const normalization. 
Fixes #805.
 2023-06-07 11:22:52 +01:00
Catherine a4402b507f hdl.dsl: py3.12+: turn off heuristic warning on ~True and ~False. 
There is now an upstream deprecation warning for the same.
We don't have to duplicate it.
 2023-06-02 13:45:15 +01:00
Catherine 58b8acac0d _toolchain.cxx: remove. 
This is causing issues on Python 3.12 and in any case should be
based on the Python `ziglang` package instead of this cursed
setuptools hack.
 2023-06-02 13:45:15 +01:00
Marcelina Kościelnicka c343e879d3 tracer: fix STORE_DEREF handling, add EXTENDED_ARG support. 
This fixes the following issues:

- on Python 3.10 and earlier, storing to free variables is now handled
  correctly
- on Python 3.11, `_varname_from_oparg` is now used, fixing problems
  with cell variables that are also arguments
- on all supported versions, EXTENDED_ARG is now parsed, ensuring proper
  handling for long functions

Fixes #792.
 2023-06-01 19:18:43 +01:00
Catherine 2a45d0e9ad lib.data: warn if a field is shadowed by an attribute of the view. 
Fixes #796.
 2023-05-31 13:27:20 +01:00
Catherine f96604f667 lib.data: make all layouts immutable. 
This is actually an existing correctness requirement (for the similar
reasons that ValueCastable.as_value() must always return the same
value every time) that for some reason wasn't respected.
 2023-05-23 23:19:29 +01:00
Catherine 7d99981d57 Implement RFC 15: Lifting shape-castable objects. 
See amaranth-lang/rfcs#15 and #784.

Note that this RFC breaks the existing syntax for initializing a view
with a new signal. Instances of `View(layout)` *must* be changed to
`Signal(layout)`.
 2023-05-15 19:42:12 +01:00
Catherine 54d5c4c047 Implement RFC 9: Constant initialization for shape-castable objects. 
See amaranth-lang/rfcs#9 and #771.
 2023-05-12 23:41:57 +01:00
Catherine 7166455a6a lib.data: implement extensibility as specified in RFC 8. 
See amaranth-lang/rfcs#8 and #772.
 2023-05-12 20:03:08 +01:00
Catherine 4398575322 lib.enum: accept any const-castable expression as member value. 
This behavior was introduced by amaranth-lang/rfcs#4. See #755.
 2023-05-12 16:39:02 +01:00
Catherine bf8bbb0f63 lib.enum: check member value shapes before subclassing. NFCI 
This commit is a preparation for accepting const-castable expressions
as enum member values.

See #755.
 2023-05-12 16:39:02 +01:00
Arusekk 5f094a23eb hdl.ast: Test *Castable subclasses on definition. 
The __init_subclass__ method fires on class definition rather than use.
It also has the bonus impact that no __new__ method is defined, so the
classes can be correctly detected as mix-in classes by modules such as
enum.
 2023-03-21 23:22:47 +00:00
Catherine 80343d1c4c hdl.ast: warn on fencepost error in Signal(range(x), reset=x). 
Also, relax the language reference inset from "warning" to "note"
since this is no longer something developers have to keep in mind
explicitly.
 2023-03-13 20:38:41 +00:00
Catherine ae1aeff0f2 lib.data: at most one Union field can have annotation with a default. 2023-03-04 09:34:50 +00:00
Catherine 16be75e02c lib.data: fix typo. 2023-03-03 09:03:53 +00:00
Catherine 0c4fda92fe hdl.ast: accept any constant-castable expression in Signal(reset=). 
See amaranth-lang/rfcs#4.

This functionality was not explicitly specified in the RFC but it
falls under "anywhere an integer or an enumeration is accepted".
 2023-03-03 06:22:56 +00:00
Catherine f77a335abf lib.enum: change shape mismatch warning category to SyntaxWarning. 2023-03-03 06:14:53 +00:00
Catherine c1b9c64e10 lib.data: ignore Python typing annotations in aggregate base class. 2023-03-03 03:45:12 +00:00
Catherine 14e73a73de hdl.ast: do not cast comparand to shape in Shape.__eq__. 
This doesn't match how other Python comparison operators work.
E.g. `1 == int("1")` but `1 != "1"`.
 2023-02-28 15:52:50 +00:00
Catherine 35561ea11a lib.data: improve reset value handling for Union. 
* Reject union initialization with more than one reset value.
* Replace the reset value specified in the class definition with
  the one provided during initalization instead of merging.
 2023-02-28 15:38:20 +00:00
Catherine c7ef05c894 lib.data: improve annotation handling for Struct and Union. 
* Annotations like `s: unsigned(4) = 1` are recognized and
  the assigned value is used as the reset value for the implicitly
  created `Signal`.
* Base classes inheriting from `Struct` and `Union` without
  specifying a layout are recognized.
* Classes that both inherit from a base class with a layout and
  specify a layout are rejected.
 2023-02-28 15:38:18 +00:00
Catherine 0ee5de036c hdl.ast: deprecate Sample, Past, Rose, Fell, Stable. 
See #526.
 2023-02-28 14:30:04 +00:00
Catherine 57612f1dce lib.enum: add Enum wrappers that allow specifying shape. 
See #756 and amaranth-lang/rfcs#3.
 2023-02-28 13:00:41 +00:00
Catherine ef2e9fa809 hdl.ast: Value.matches() with no arguments should return C(1). 
The behavior of the following must be always the same:
- `with m.Switch(v): with m.Case(*pats):`
- `with m.If(v.matches(*pats)):`
 2023-02-28 09:09:27 +00:00
Catherine 58721ee4fe hdl: implement constant-castable expressions. 
See #755 and amaranth-lang/rfcs#4.
 2023-02-27 22:38:38 +00:00
Catherine bef2052c1e hdl.ast: implement Value.__pos__. 2023-02-27 22:31:17 +00:00
Catherine fcc4f54367 lib.data: make Field() immutable. 
Mutability of Field isn't specified by the RFC and can cause issues
if the objects stored in Layout subclasses are mutated. There isn't
any reason to do that (the subclasses themselves are mutable and
handle that correctly), so disallow it.
 2023-02-21 17:58:28 +00:00
Catherine 7e3e10e733 lib.data: implement RFC 1 "Aggregate data structure library". 
See amaranth-lang/rfcs#1.
 2023-02-15 10:10:01 +00:00
Catherine 5a79c351e3 Remove features deprecated in version 0.3. 2023-01-31 21:38:27 +00:00
Catherine 7044e09110 hdl.ast: remove Shape<>tuple comparisons. 
See #691.

I missed this in commit 29502442.
 2023-01-31 15:23:06 +00:00
Catherine 29502442fb hdl.ast: remove Shape<>tuple casts. 
Closes #691.
 2023-01-31 12:58:29 +00:00
Arusekk de6b69370f hdl.ast: Do not warn on int Enums in Cat. 
This aligns with the behavior for plain Enums.
 2023-01-22 23:40:39 +00:00
Arusekk 58a0c68279 hdl.ast: allow typed int enums in Value.cast. 2023-01-22 23:40:39 +00:00
Catherine da26f1c915 hdl,back,sim: accept .as_signed() and .as_unsigned() on LHS. 
These operators are ignored when they are encountered on LHS, as
the signedness of the assignment target does not matter in Amaranth.
.as_signed() appears on LHS of assigns to signed aggregate fields.
 2022-09-24 07:19:47 +00:00
Catherine bf16acf2f0 hdl.ast: implement ShapeCastable (like ValueCastable). 
Refs #693.
 2022-09-24 07:19:03 +00:00
Catherine 0723f6bac9 hdl.ast: recursively cast ValueCastable objects to values. 2022-09-24 07:18:57 +00:00
Bastian Löher 02364a4fd7 sim: Fix clock phase in add_clock having to be specified in ps. 2022-02-04 16:46:52 +00:00
Irides 538c14116c sim.pysim: use "bench" as a top level root for testbench signals. 
Fixes #561.
 2021-12-16 15:46:05 +00:00
Catherine 847e46927b back.{verilog,rtlil}: fix commit d83c4a1b. 
The `ports` argument has been passed implicitly, via `**kwargs`, and
that was broken during the deprecation.

Closes #659.
 2021-12-14 10:47:04 +00:00
Irides d83c4a1b21 back.{rtlil,verilog}: deprecate implicit ports. 
Fixes #630.
 2021-12-13 12:21:44 +00:00
modwizcode 1ee2482c6b sim: represent time internally as 1ps units 
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.

Fixes #535.
 2021-12-13 08:15:11 +00:00
whitequark 7c161957bf build.dsl: check type of resource number. 
Fixes #599.
 2021-12-11 13:37:15 +00:00
whitequark 7e2b72826f sim.core: warn when driving a clock domain not in the simulation. 
Closes #566.
 2021-12-11 13:22:24 +00:00
whitequark ac13a5b3c9 sim._pyrtl: reject very large values. 
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
 2021-12-11 13:00:46 +00:00
whitequark 599615ee3a hdl.ir: reject elaboratables that elaborate to themselves. 
Fixes #592.
 2021-12-11 12:40:05 +00:00
whitequark 66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names. 
Closes #595.
 2021-12-11 11:12:25 +00:00
whitequark b452e0e871 hdl.ast: support division and modulo with negative divisor. 
Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
 2021-12-11 10:25:48 +00:00
whitequark 44b8bd29af hdl.ast: warn on bare integer value used in Cat()/Repl(). 
Fixes #639.
 2021-12-11 08:18:33 +00:00