Commit graph

226 commits

Author SHA1 Message Date
Catherine
0cb71f8c57 sim: only preempt testbenches on explicit wait.
Before this commit, testbenches (generators added with `add_testbench`)
were not only preemptible after any `yield`, but were *guaranteed* to
be preempted by another testbench after *every* yield. This is evil:
if you have any race condition between testbenches, which is common,
this scheduling strategy will maximize the resulting nondeterminism by
interleaving your testbench with every other one as much as possible.
This behavior is an outcome of the way `add_testbench` is implemented,
which is by yielding `Settle()` after every command.

One can observe that:
- `yield value_like` should never preempt;
- `yield assignable.eq()` in `add_process()` should not preempt, since
  it only sets a `next` signal state, or appends to `write_queue` of
  a memory state, and never wakes up processes;
- `yield assignable.eq()` in `add_testbench()` should only preempt if
  changing `assignable` wakes up an RTL process. (It could potentially
  also preempt if that wakes up another testbench, but this has no
  benefit and requires `sim.set()` from RFC 36 to be awaitable, which
  is not desirable.)

After this commit, `PySimEngine._step()` is implemented with two nested
loops instead of one. The outer loop iterates through every testbench
and runs it until an explicit wait point (`Settle()`, `Delay()`, or
`Tick()`), terminating when no testbenches are runnable. The inner loop
is the usual eval/commit loop, running whenever a testbench changes
design state.

`PySimEngine._processes` is a `set`, which doesn't have a deterministic
iteration order. This does not matter for processes, where determinism
is guaranteed by the eval/commit loop, but causes racy testbenches to
pass or fail nondeterministically (in practice depending on the memory
layout of the Python process). While it is best to not have races in
the testbenches, this commit makes `PySimEngine._testbenches` a `list`,
making the outcome of a race deterministic, and enabling a hacky work-
around to make them work: reordering calls to `add_testbench()`.

A potential future improvement is a simulation mode that, instead,
randomizes the scheduling of testbenches, exposing race conditions
early.
2024-03-24 11:53:18 +00:00
Catherine
6ce82848d9 lib.memory: Memory.{r,w}_ports.{read,write}_ports.
The abbreviated form was initially added to match `lib.fifo`, but it
looks very out of place on `lib.memory`, and we may be moving away from
such heavy use of abbreviations anyway.

While technically a breaking change, these attributes have very narrow
usefulness and so this change qualifies as "minor".
2024-03-22 23:05:42 +00:00
Catherine
2333c5f0af lib.memory: expand Memory.Init.__repr__().
Display `shape` and `depth` also. `depth` is redundant although useful
for ease of reading (there are always `depth` elements shown), but
`shape` was just lost.
2024-03-22 23:05:42 +00:00
Catherine
fc84b8decf lib.memory: remove Memory.Init.depth.
This attribute is fully redundant with `.__len__()`, and is out of place
on a `list`-like container like `Memory.Init`.

The `.shape` attribute, however, provides a unique function.
2024-03-22 23:05:42 +00:00
Catherine
b8b1e7081b lib.memory: improve and regularize diagnostics. 2024-03-22 23:05:42 +00:00
Catherine
8d44ec513d lib.memory: improve and finish documentation. 2024-03-22 23:05:42 +00:00
Wanda
456dcaeb7b lib.io: Implement *Buffer from RFC 55. 2024-03-22 01:44:25 +00:00
Wanda
8c65a79cdd hdl._ir: Remove support for non-Elaboratable elaboratables.
Fixes #1216.
2024-03-20 08:20:23 +00:00
Wanda
d6bf47d549 Implement RFC 51: Add ShapeCastable.from_bits and amaranth.lib.data.Const.
Co-authored-by: Catherine <whitequark@whitequark.org>
2024-03-19 04:01:26 +00:00
Wanda
598cf8db28 lib.io: Implement *Port from RFC 55. 2024-03-18 23:56:34 +00:00
Wanda
744576011f Implement RFC 53: Low-level I/O primitives.
Co-authored-by: Catherine <whitequark@whitequark.org>
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
2024-03-18 20:33:22 +00:00
Wanda
18b54ded0a hdl._ir: Fix fallout from #1190, add more tests. 2024-03-16 14:17:00 +00:00
Wanda
23f1b63425 lib.memory: Add Signature.create implementations. 2024-03-16 08:48:32 +00:00
Catherine
11ec35d258 lib.wiring: remove unnecessary flipping in Signature.flatten. 2024-03-15 10:35:50 +00:00
Wanda
49dee891e8 tests: Exorcise some star-imports. 2024-03-13 18:03:22 +00:00
mcc
27ca96383e utils: F-strings are missing the letter "f"
Also adds tests for utils ValueError strings.
2024-03-13 14:56:27 +00:00
Wanda
455a7bc6c8 lib.memory: Allow setting Memory.init.
The `init` property is already mutable, so this adds no actual new
functionality, just convenience.
2024-03-13 13:12:15 +00:00
Wanda
cb96b15b8c hdl._ir: Remove all support for fragment flattening. 2024-03-11 21:28:46 +00:00
Wanda
bfe541a6d7 Implement RFC 50: Print and string formatting.
Co-authored-by: Catherine <whitequark@whitequark.org>
2024-03-11 09:42:43 +00:00
Wanda
127fe1fd2e hdl._xfrm: Get rid of _insert_resets, move the logic downstream. 2024-03-03 19:34:35 +00:00
Wanda
ea561378ac hdl._nir: Remove ArrayMux, use AssignmentList instead. 2024-03-03 18:52:21 +00:00
Wanda
fc9369b8e1 hdl._xfrm: Simplify EnableInserter logic. 2024-03-03 18:38:20 +00:00
Wanda
7d295b040a test_hdl_ir: Add a bunch of tests for NIR emitter. 2024-03-03 18:09:08 +00:00
Wanda
2400d39730 lib.io: Make Pin.name return the whole path.
This prevents duplicate pin names.
2024-02-29 20:32:43 +00:00
Wanda
76a7dc396c hdl._ir: Handle duplicate fragment names. 2024-02-29 20:03:38 +00:00
Wanda
047b64d02c test_hdl_ir: Add NIR testcases for Instance. 2024-02-29 19:39:20 +00:00
Wanda
2bf1b4dafc hdl._ast: Make AST nodes immutable.
Fixes #1067.
2024-02-29 18:56:46 +00:00
Wanda
f8e2d26b8f hdl._ir: Inline AssignmentLegalizer into netlist building.
Fixes #1150.
2024-02-28 15:15:42 +00:00
Wanda
f2dab705ee lib.io: Expose Pin path and name as attributes. 2024-02-28 11:49:35 +00:00
Wanda
1dd2e6150c lib.io: Add missing __repr__ to signature type. 2024-02-28 09:11:53 +00:00
Wanda
8af9fe2606 lib.memory: Add missing __eq__ to signature types. 2024-02-28 09:06:49 +00:00
Wanda
c6bc9b47ef hdl.ir: add IOBufferInstance. 2024-02-27 18:56:24 +00:00
Wanda
85bb5ee77c hdl._dsl: Change FSM codegen to avoid mutating AST nodes.
Fixes #1066.
2024-02-27 16:20:25 +00:00
Wanda
f524dd041a lib.io, build.res: Make Pin and related objects interfaces.
Fixes #1040.
2024-02-27 11:40:25 +00:00
Wanda
751e0f4b57 ir: kill Fragment.ports 2024-02-27 08:26:30 +00:00
Amelia Cuss
a586df89ad lib.wiring.connect: diagnostic when no connection made.
If a connect() call results in no connections being made, and it's
because there were no outputs specified at all, issue an error.
Tests enumerate cases per
https://github.com/amaranth-lang/amaranth/pull/1153#issuecomment-1962810678.

Co-authored-by: Catherine <whitequark@whitequark.org>
2024-02-25 09:33:46 +00:00
Catherine
09029cdd91 hdl._ir: remember origins of a fragment during elaboration.
This isn't expected to result in a significant increase in memory use,
so for now it's enabled by default. Elaboration chains where it is not
desired to preserve origins can delete the `origins` attribute from
the fragment and nothing will be stored.

The interface `Fragment.origins` remains private, as is the rest of
the `Fragment` interface (including itself), but it enables certain
codebases that currently use a much more invasive technique to rely on
reading a single private field.
2024-02-22 19:03:55 +00:00
Amelia Cuss
c40cfc9fb5 lib.enum: honor enum.nonmember.
Use _EnumDict._member_names to determine which members to consider.
This way we don't need to redo sunder/dunder checks, and `nonmember`s
(introduced in py3.11) are correctly excluded.

This is a defacto public API, given it remains usable from py3.8
until py3.12 inclusive.  (_member_names changes from a list to a
keys-only dict for performance reasons in py3.11, but they iterate the
same.) In current Python main (i.e. what will most likely be 3.13), a
"member_names" property is added which returns those keys.
2024-02-19 23:06:22 +00:00
Wanda
890e099ec3 Implement RFC 45: Move hdl.Memory to lib.Memory. 2024-02-19 22:24:58 +00:00
Wanda
6d65dc1366 hdl, back.rtlil: track and emit module/submodule locations. 2024-02-19 21:41:32 +00:00
Wanda
6058ad35cf hdl._ast: make Shape immutable and hashable.
Fixes #1127.
2024-02-16 15:21:05 +00:00
Wanda
24a392887a Implement RFC 43: Rename reset= to init=. 2024-02-15 22:52:24 +00:00
Wanda
e3324e1456 hdl._dsl: fix using 0-width Switch with integer keys.
Fixes #1133.
2024-02-14 19:13:14 +00:00
Wanda
5ffb48b5fb hdl._ast: fix using 0-width Switch with integer keys.
This comes up in `AssignmentLegalizer`-produced `Switch`es for
`ArrayProxy`.
2024-02-14 11:52:35 +00:00
Wanda
0ecd06a7e5 sim: fix using 0-width Switch. 2024-02-14 11:51:19 +00:00
Wanda
0da439cce1 hdl._ast: deprecate ValueCastable.lowermethod. 2024-02-13 05:06:06 +00:00
Wanda
e2fd819742 hdl._ast: fix shift_right and as_signed edge cases. 2024-02-13 04:52:38 +00:00
Catherine
0056e982c5 docs/reference: document Value, ValueCastable, ValueLike.
Co-authored-by: Wanda <wanda@phinode.net>
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
2024-02-13 03:22:04 +00:00
Wanda
4014f6429c Implement RFC 27 amendment: deprecate add_sync_process, not add_process. 2024-02-12 18:26:48 +00:00
Wanda
2d42d649ee tests: stop using implicit ports. 2024-02-12 13:24:54 +00:00