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Author SHA1 Message Date
whitequark 8686e9aa06 back.pysim: give better names to unnamed fragments and their signals. 
Was: top.#0, top.None_clk
Now: top.U0, top.U0_clk

(U for Unnamed, or similarly, an unit refdes.)
 2019-01-26 18:07:16 +00:00
whitequark b133eb735f back.rtlil: accept any elaboratable, not just fragments. 2019-01-26 16:11:29 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark 7b25665fde back.pysim: fix behavior of initial cycle for sync processes. 
The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.
 2019-01-25 20:37:56 +00:00
whitequark 12e04e4ee5 back.pysim: wake up processes before ever committing any values. 
Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
 2019-01-21 16:00:25 +00:00
whitequark b50b47d984 hdl.ast: give Assert and Assume their own src_loc. 
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
 2019-01-19 00:08:51 +00:00
whitequark 66466a8a0e back.rtlil: only emit each AnyConst/AnySeq cell once. 
These are semantically like signals, not like constants.
 2019-01-18 01:34:48 +00:00
whitequark 198efcad31 hdl.xfrm: add SampleLowerer. 2019-01-17 01:41:02 +00:00
whitequark f2425001aa back.rtlil: slightly nicer naming for $next signals. NFC. 2019-01-16 17:20:38 +00:00
whitequark 935bf2d8cf back.rtlil: rename \sig$next to $next$sig. 
These used to serve a useful purpose being public, back when the RTLIL
backend was immature. Not anymore; now they merely clutter up views
in gtkwave and so on.
 2019-01-16 14:51:20 +00:00
whitequark 6191760c30 Unbreak 655d02d5. 2019-01-15 23:09:10 +00:00
William D. Jones 655d02d5b8 back.rtlil: Generate $anyconst and $anyseq cells. 2019-01-15 22:52:45 +00:00
William D. Jones 77728c2dea hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children. 2019-01-15 22:52:45 +00:00
whitequark cbf7bd6e31 back.pysim: handle non-driven, non-port signals. 
Fixes #20.
 2019-01-13 08:31:38 +00:00
whitequark 06faeee357 back.verilog: better error message if Yosys is not found. 
Fixes #17.
 2019-01-13 08:10:23 +00:00
whitequark 307de722cb back.verilog: remove undriven check. 
This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.

Fixes #23.
 2019-01-08 22:43:09 +00:00
Adam Greig 560bb007cc Give the top level scope a name to fix VCD hierarchy. 2019-01-06 00:10:37 +00:00
whitequark ef1e0b8d55 back.rtlil: translate empty slices correctly. 2019-01-02 18:14:29 +00:00
William D. Jones f31055a4ef back.rtlil: Generate RTLIL for Assert/Assume statements. 2019-01-02 11:17:39 +00:00
William D. Jones f77dc40256 hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children. 2019-01-02 11:17:39 +00:00
whitequark 1a9dcd2f28 back.rtlil: fix typo. 2019-01-01 08:50:28 +00:00
whitequark ae3c5834ed back.rtlil: match shape of Array elements to ArrayProxy shape. 
Fixes #15.
 2018-12-31 03:43:34 +00:00
whitequark cdc40eaa9b back.rtlil: fix typo. 2018-12-31 03:37:38 +00:00
whitequark 849c649259 back.pysim: warn if simulation is not run. 
This would have prevented 3ea35b85.
 2018-12-29 15:02:04 +00:00
whitequark 92a96e1644 hdl.rec: add basic record support. 2018-12-28 13:22:10 +00:00
whitequark fe8cb55204 lib.cdc: add tests for MultiReg. 2018-12-26 12:58:30 +00:00
whitequark b4fbef65ca back.rtlil: clarify $verilog_initial_trigger behavior. NFC. 2018-12-26 06:45:57 +00:00
whitequark 010ddb96b5 back.rtlil: unbreak d47c1f8a. 2018-12-24 19:11:07 +00:00
whitequark d47c1f8a8a back.rtlil: use one $meminit cell, not one per word. 
This is *far* more efficient.
 2018-12-24 11:53:58 +00:00
whitequark 98f554aa08 hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. 
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
 2018-12-24 02:17:28 +00:00
whitequark 1c7c75a254 hdl.xfrm: implement SwitchCleaner, for pruning empty switches. 2018-12-24 02:02:59 +00:00
whitequark fc0fb9d89f back.rtlil: always output negative values as two's complement. 
- is valid in RTLIL but means something entirely different.
 2018-12-24 01:38:32 +00:00
whitequark 5702767263 back.rtlil: emit dummy logic to work around Verilog deficiencies. 2018-12-23 10:14:42 +00:00
whitequark 9faa1d3742 back.rtlil: do not translate empty fragments. 
The resulting Verilog confuses some frontends.
 2018-12-23 09:20:02 +00:00
whitequark 45a474788c back.rtlil: only translate switch tests once. 
This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
 2018-12-23 07:17:52 +00:00
whitequark 2b6ddbb713 back.rtlil: fix swapped operands in mux codegen. 2018-12-23 06:47:38 +00:00
whitequark 59c7540aeb back.rtlil: split processes as finely as possible. 
This makes simulation work correctly (by introducing delta cycles,
and therefore, making the overall Verilog simulation deterministic)
at the price of pessimizing mux trees generated by Yosys and Synplify
frontends, sometimes severely.
 2018-12-22 10:03:16 +00:00
whitequark d29929912f back.rtlil: remove useless condition. NFC. 2018-12-22 07:24:15 +00:00
whitequark 98a9744be4 hdl.xfrm: Abstract*Transformer→*Visitor 2018-12-22 06:03:39 +00:00
whitequark 37b81309d3 back.rtlil: always initialize the entire memory. 
This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.
 2018-12-22 05:27:42 +00:00
whitequark 6ee80408bb back.verilog: do not rename internal signals. 
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
 2018-12-22 00:53:40 +00:00
whitequark 48d13e47ec back.pysim: handle out of bounds ArrayProxy indexes. 2018-12-21 12:32:08 +00:00
whitequark 7ae7683fed back.pysim: give numeric names to unnamed subfragments in VCD. 2018-12-21 12:29:33 +00:00
whitequark a40e2cac4b back.pysim: fix an issue with too few funclet slots. 2018-12-21 10:25:28 +00:00
whitequark a061bfaa6c hdl.mem: tie rdport.en high for asynchronous or transparent ports. 2018-12-21 04:22:16 +00:00
whitequark 8d58cbf230 back.rtlil: more consistent prefixing for subfragment port wires. 2018-12-21 04:21:11 +00:00
whitequark 2b4a8510ca back.rtlil: implement memories. 2018-12-21 01:55:59 +00:00
whitequark 6672ab2e3f back.rtlil: explicitly pad constants with zeroes. 
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
 2018-12-21 01:51:18 +00:00
whitequark 221f108fbe back.rtlil: fix translation of Cat. 2018-12-21 01:48:02 +00:00
whitequark f7fec804ec ir: allow non-Signals in Instance ports. 2018-12-20 23:40:40 +00:00