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Author SHA1 Message Date
whitequark 9893e3c044 lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions. 
Refs #97.
 2019-09-12 13:48:45 +00:00
whitequark 8f659b6cd6 lib.cdc: adjust MultiReg for new CDC primitive conventions. 
Refs #97.
 2019-09-12 13:48:24 +00:00
whitequark 8c30147e39 build.plat,vendor: allow clock constraints on arbitrary signals. 
Currently only done for Synopsys based toolchains (i.e. not nextpnr).

Refs #88.
 2019-09-11 23:35:43 +00:00
whitequark d1779bdb59 back: return name map from convert_fragment(). 2019-09-11 23:22:12 +00:00
whitequark 7342662bee hdl.ast: warn if reset value is truncated. 
Fixes #183.
 2019-09-10 07:26:34 +00:00
Darrell Harmon 27cedf4302 vendor.lattice_ecp5: pass ecppack_opts to ecppack. 2019-09-10 03:32:36 +00:00
whitequark 9b398b502e hdl.ast: check type of Sample(domain=...). 
Fixes #199.
 2019-09-08 23:55:05 +00:00
whitequark 3f6abc0b7a hdl.dsl: add Default(), an alias for Case() with no arguments. 
Fixes #197.
 2019-09-08 12:24:18 +00:00
whitequark eb04a2509e hdl.mem,lib,examples: use Signal.range(). 2019-09-08 12:19:13 +00:00
whitequark ccfbccc044 hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...). 
Fixes #196.
 2019-09-08 12:10:31 +00:00
whitequark 5e9587bbbd Remove nmigen.lib from prelude. 
Currently it's just MultiReg, and there's no particularly good reason
to privilege this specific CDC primitive so much.
 2019-09-06 06:53:06 +00:00
whitequark 284b533995 setup: replace versioneer with setuptools_scm. 
Has the same problems with git-archive but is much less invasive.
 2019-09-06 05:20:42 +00:00
whitequark 943ce317af hdl.ast,back.rtlil: implement Cover. 
Fixes #194.
 2019-09-03 01:32:24 +00:00
whitequark 2e20622046 hdl.cd: add negedge clock domains. 
Fixes #185.
 2019-08-31 22:05:48 +00:00
Emily c4e8ac734f _toolchain,build.plat,vendor.*: add required_tools list and checks. 2019-08-31 00:05:47 +00:00
whitequark 4e91710933 vendor.lattice_ecp5: drive GSR synchronous to user clock by default. 
Fixes #167.
 2019-08-30 14:26:49 +00:00
whitequark a4b58cbf3a build.dsl: allow both str and int resource attributes. 2019-08-30 08:35:52 +00:00
Emily 98278a044d test.tools: use _toolchain.get_tool. 2019-08-28 11:52:16 +00:00
whitequark b14f5572d8 _toolchain: new module, for injecting dependencies in e.g. Nix. 2019-08-28 11:32:18 +00:00
whitequark 2168ff512b back.verilog: bump Yosys version requirement to 0.9. 
Fixes #55.
 2019-08-26 09:59:40 +00:00
whitequark b4b5d9e2ef vendor.lattice_ecp5: revert default toolchain to Trellis. 
This was unintentionally changed in 7fc1058e.
 2019-08-25 08:07:00 +00:00
whitequark 72cf4ca991 back.pysim: implement sim.add_clock(if_exists=True). 2019-08-23 08:53:48 +00:00
whitequark 906385c7f8 back.pysim: don't crash when trying to drive a nonexistent domain clock. 2019-08-23 08:37:59 +00:00
whitequark 9350620f89 build.run: add BuildPlan.digest(), useful for caching. 2019-08-23 01:10:51 +00:00
whitequark 7fc1058ed2 vendor.lattice_ecp5: add Diamond support. 2019-08-22 21:36:24 +00:00
whitequark c77274c1ad vendor: eliminate unnecessary LUT instantiation. 
Fixes #165.
 2019-08-22 21:29:20 +00:00
whitequark 47bad3d20e back.rtlil: print real parameters with maximum precision. 2019-08-22 04:42:30 +00:00
Darrell Harmon aefde85031 back.rtlil: add support for real (float) parameters on Instances. 
Required for Xilinx MMCME2_BASE, etc.
 2019-08-22 04:13:05 +00:00
Darrell Harmon 6737ef79f9 vendor.xilinx_series7: use STARTUPE2, not STARTUPE3. 
STARTUPE3 is for Ultrascale.
 2019-08-21 22:25:55 +00:00
whitequark 5889e62668 vendor.lattice_ice40: remove --placer heap default option. 
It is not the place of nMigen to decide on this default, since both
SA and HeAP have valid uses that are not covered by the other.
 2019-08-21 21:32:38 +00:00
whitequark 531040d2fd vendor: style. NFC. 2019-08-21 21:32:36 +00:00
whitequark 25b280dba1 build.plat: remove TemplatedPlatform.unix_interpreter. 
Vendor toolchains generally require far more workarounds than this,
and we already have a perfectly fine way of overriding templates.
 2019-08-21 21:02:13 +00:00
whitequark 1fc63a62c0 back.pysim: allow coroutines as processes. 
This is a somewhat obscure use case, but it is possible to use async
functions with pysim by carefully using @asyncio.coroutine. That is,
async functions can call back into pysim if they are declared in
a specific way:

  @asyncio.coroutine
  def do_something(self, value):
    yield self.reg.eq(value)

which may then be called from elsewhere with:

  async def test_case(self):
    await do_something(0x1234)

This approach is unfortunately limited in that async functions
cannot yield directly. It should likely be improved by using async
generators, but supporting coroutines in pysim is unobtrustive and
allows existing code that made use of this feature in oMigen to work.
 2019-08-21 03:30:37 +00:00
William D. Jones c934fc66e9 test.test_examples: Convert pathlib-specific class to string. 
subprocess.check_call iterates over its arguments to check for spaces
and tabs, and on Windows, the pathlib-specific WindowsPath is not
iterable.
 2019-08-20 00:54:10 +00:00
whitequark 5ad409e897 back.verilog: parse output of yosys -V. 
See #55.
 2019-08-19 23:28:33 +00:00
whitequark 7ca29a5748 Fix nmigen.__version__ to work on git-archive artifacts. 
Fixes #137.
 2019-08-19 23:14:41 +00:00
whitequark 13316053e3 build.plat, hdl.ir: coordinate missing domain creation. 
Platform.prepare() was completely broken after addition of local
clock domains, and only really worked before by a series of
accidents because there was a circular dependency between creation
of missing domains, fragment preparation, and insertion of pin
subfragments.

This commit untangles the dependency by adding a separate public
method Fragment.create_missing_domains(), used in build.plat.

It also makes DomainCollector consider both used and defined domains,
such that it will work on fragments before domain propagation, since
create_missing_domains() can be called by user code before prepare().

The fragment driving missing clock domain is not flattened anymore,
because flattening does not work well combined with local domains.
 2019-08-19 22:52:01 +00:00
whitequark 77012fc143 vendor.lattice_ice40: use a local clock domain in create_missing_domain(). 2019-08-19 21:46:44 +00:00
whitequark a069d975b2 lib.cdc: use a local clock domain in ResetSynchronizer. 
This reverts commit 779f3ee906.
This reverts commit 300d47ca2e.
This reverts commit 9c54d0c061.
 2019-08-19 21:45:08 +00:00
whitequark 003ba3b45f hdl.cd: implement local clock domains. 
Closes #175.
 2019-08-19 21:44:33 +00:00
whitequark 9bdadbff09 back.pysim: index domains by identity, not by name. 
Changed in preparation for introducing local clock domains.
 2019-08-19 21:44:33 +00:00
whitequark 69d36dc139 hdl.xfrm: lower resets in DomainLowerer as well. 
Changed in preparation for introducing local clock domains.

Also makes elaboration about 15% faster.
 2019-08-19 21:44:30 +00:00
whitequark 404f99f022 hdl.xfrm: consider fragment's own domains in DomainLowerer. 
Changed in preparation for introducing local clock domains.
 2019-08-19 21:07:02 +00:00
whitequark 32bfbb11cb formal→asserts 
Closes #171.
 2019-08-19 20:23:24 +00:00
whitequark 2770db6de8 tracer: fix typo. 
Introduced in 62b3e366.
 2019-08-19 20:20:18 +00:00
whitequark ada1d6a603 build.plat: do not prepare fragments twice. 
Fixes #169.
 2019-08-19 19:49:51 +00:00
whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). 
Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.
 2019-08-19 19:49:51 +00:00
Robin Heinemann 8e048c5a7c build.dsl: add conn argument to Connector. 2019-08-18 19:56:25 +00:00
whitequark 84f2c3df2b compat.fhdl.decorators: avoid using deprecated NativeCEInserter. 2019-08-18 16:27:11 +00:00
whitequark d44ea4e9fe hdl.xfrm: make deprecated CEInserter more well-behaved. 2019-08-18 16:26:45 +00:00
whitequark ed7e07c6c1 hdl.ast: implement Initial. 
This is the last remaining part for first-class formal support.
 2019-08-15 02:53:07 +00:00
whitequark 40abaef858 hdl.xfrm: sample cache should be per-fragment. 2019-08-15 02:45:31 +00:00
whitequark fa0fa056ba hdl.xfrm: CEInserter→EnableInserter. 
Fixes #166.
 2019-08-12 13:39:26 +00:00
whitequark 9d2cbbabb8 hdl.ast: hash-cons ValueKey. 
This speeds up elaboration by ~10%.
 2019-08-08 10:56:53 +00:00
whitequark 4ee82c9584 tracer: use sys._getframe directly. 
This speeds up elaboration by ~30-40%.
 2019-08-08 10:23:35 +00:00
whitequark e6b1e3de1a compat.fhdl.decorators: port from oMigen. 2019-08-08 08:09:28 +00:00
whitequark 5c626e33bf compat.fhdl.module: fix finalization of transformed compat submodules. 
Before this commit, the TransformedElaboratable of a CompatModule
would be ignored, and .get_fragment() would be used to retrieve
the CompatModule within.

After this commit, the finalization process is reworked to match
oMigen's finalization closely, and all submodules, native and compat,
are added in the same way that preserves applied transforms.
 2019-08-08 07:45:34 +00:00
whitequark 1b379a513c vendor.lattice_ice40: add iCE5LP2K support. 2019-08-07 09:25:20 +00:00
whitequark cfbc678508 vendor.lattice_ice40: add iCE40UP3K support. 2019-08-07 09:06:27 +00:00
whitequark 9c35e44e4a vendor.lattice_ice40: add iCE5LP1K support. 2019-08-07 09:01:11 +00:00
whitequark 434b686d5e vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic. 
On Xilinx devices, flip-flops are reset to their initial state with
an internal global reset network, but this network is deasserted
asynchronously to user clocks. Use BUFGCE and STARTUP to hold default
clock low until after GWE is deasserted.
 2019-08-04 23:28:09 +00:00
whitequark 3d7214cb70 vendor.xilinx_spartan_3_6: reconsider bitgen defaults. 
Previously changed in 27063a3b.

I haven't realized the .bin file is the same as the .bit file without
a small header. That means generating it is free and it's just easier
to let programming tools to be able to always rely on its existence.
 2019-08-04 23:28:09 +00:00
whitequark 27063a3bd3 vendor.xilinx_spartan_3_6: set bitgen defaults to -g Binary:Yes -g Compress. 
* `-g Binary:Yes` should be overridable.
  * `-g Compress` is a good default.
 2019-08-04 14:18:49 +00:00
whitequark 65da905c15 vendor.xilinx_spartan_3_6: always use -w for map/par/bitgen. 
-w stands for "override output file", and supplying user options
should not remove it.
 2019-08-04 14:12:02 +00:00
whitequark 15e8dfe532 vendor.xilinx_spartan_3_6: do not use retiming by default. 
This was added in b404d603, probably by mistake, and is certainly
wrong given that we do not (yet) correctly mark CDC FFs.
 2019-08-04 13:48:33 +00:00
whitequark 6b025df12c vendor.xilinx_spartan_3_6: force use of bash on UNIX. 2019-08-04 13:20:54 +00:00
whitequark 5eb4e2ee51 build.plat: allow selecting a specific UNIX shell interpreter. 
Mostly because vendor tools have bashisms.
 2019-08-04 13:20:54 +00:00
whitequark 34a97b2751 vendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins. 2019-08-04 00:30:50 +00:00
whitequark 2e6627c4af back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS. 
Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
and when it doesn't, it causes Yosys to produce invalid Verilog.
Using a dummy wire is always safe and is not a major readability
issue as this is a rare corner case.

(It is not trivial to shorten the RHS in this case, because during
expansion of an ArrayProxy, match_shape() could be called in
a context far from the RHS handling logic.)
 2019-08-04 00:12:08 +00:00
whitequark d0ac8bf789 back.rtlil: actually match shape of left hand side. 
This comes up in code such as:
  Array([Signal(1), Signal(8)]).eq(Const(0, 8))
 2019-08-03 23:48:28 +00:00
whitequark 999a2f612a vendor.lattice_ice40: add missing signal indexing. 2019-08-03 22:59:33 +00:00
whitequark 8dd54ac544 build.run: use keyword-only arguments where appropriate. 2019-08-03 22:52:58 +00:00
whitequark 0fe05188e8 compat.fhdl.specials: track changes in build.plat. 2019-08-03 22:52:34 +00:00
whitequark 99d205494a hdl.dsl: reword m.If(~True) warning to be more clear. 
Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.
 2019-08-03 18:52:24 +00:00
whitequark 8854ca03ae build.plat,vendor: automatically create sync domain from default_clk. 
But only if it is not defined by the programmer.

Closes #57.
 2019-08-03 18:36:58 +00:00
whitequark e0b54b417e hdl.ir: allow adding more than one domain in missing domain callback. 
This is useful for injecting complex power-on reset logic.
 2019-08-03 18:19:40 +00:00
whitequark 9c28b61d9f hdl.ir: don't expose as ports missing domains added via elaboratables. 
The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
 2019-08-03 16:39:21 +00:00
whitequark 21f2f8c46e build.plat: add default_rst, to be used with default_clk. 2019-08-03 16:28:03 +00:00
whitequark 4dbb5352ad build.plat: add default_clk{,_constraint,_frequency}. 
This is the equivalent of oMigen's default_clk and default_clk_period
except the period is taken from the resource.
 2019-08-03 16:18:46 +00:00
whitequark cea92e9531 hdl.ir: allow returning elaboratables from missing domain callback. 
This allows e.g. injecting a clock/reset generator in platform build
code on demand (i.e. if the domain is not instantiated manually).

See #57.
 2019-08-03 15:44:02 +00:00
whitequark fc846532c7 hdl.ir: raise DomainError if a domain is used but not defined. 
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
 2019-08-03 15:31:24 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. 
See #57.
 2019-08-03 14:54:20 +00:00
whitequark ace2b5ff0a hdl.dsl: warn on suspicious statements like m.If(~True):. 
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.

Fixes #159.
 2019-08-03 14:00:29 +00:00
whitequark ab5426ce74 Improve test added in 29fee01f to not leak warnings. 2019-08-03 13:44:44 +00:00
whitequark ee03eab52f back.rtlil: fix sim-synth mismatch with assigns following switches. 
Closes #155.
 2019-08-03 13:27:47 +00:00
whitequark 0a603b3844 hdl.ast: fix typo. 2019-08-03 13:21:09 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select. 
Fixes #148.
 2019-08-03 13:07:06 +00:00
whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. 
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.

Also fixes incorrect source location on value.part().
 2019-08-03 12:51:57 +00:00
whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None. 
Fixes #164.
 2019-08-03 12:30:39 +00:00
whitequark 995e4adb8c hdl.xfrm: handle mem.{Read,Write}Port in CEInserter. 
Fixes #154.
 2019-07-31 05:20:05 +00:00
N. Engelhardt 5fd8a796ae vendor: don't emit duplicate iobuf submodule names. 
These are no longer allowed after commit 698b005.
 2019-07-21 07:49:21 +00:00
N. Engelhardt 698b005182 hdl.dsl: add getters to m.submodules. 2019-07-19 12:39:47 +00:00
Alain Péteut 81e59832fb lib.fifo: fix typo. 2019-07-15 14:12:33 +00:00
Staf Verhaegen ff343d5cf0 Pin: Add extra hierarchy level for name derivation 2019-07-14 19:30:12 +00:00
William D. Jones b963449b41 build.run: Ensure batch script returns proper error code. 2019-07-14 17:43:33 +00:00
whitequark ee15538cf0 back.pysim: correctly add gtkwave traces for signals with decoders. 2019-07-12 13:35:44 +00:00
William D. Jones 6ee760e83f build.dsl: Add optional name_suffix to Resource.family. 2019-07-10 15:41:23 +00:00
whitequark 278b624c66 back.pysim: avoid malformed VCD files when a decoder uses tabs. 2019-07-10 12:54:59 +00:00
whitequark 2fa858b003 hdl.ir: make UnusedElaboratable a real warning. 
Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.
 2019-07-10 12:46:54 +00:00
whitequark 37f363e338 back.rtlil: add decodings to cases when switching on a signal. 
Fixes #134.
 2019-07-09 19:48:15 +00:00
whitequark 10e56c75fb back.verilog: run proc_prune for much cleaner output. 
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@44bcb7a1.
 2019-07-09 19:28:09 +00:00
whitequark 00c5209a47 hdl.{ast,dsl},back.rtlil: track source locations for switch cases. 
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.
 2019-07-09 19:26:47 +00:00
Jacob Lifshay 62b3e36612 tracer: add PyPy support to get_var_name(). 
Fixes #141.
 2019-07-09 07:29:01 +00:00
whitequark 367ad5aee7 build.dsl: add Resource.family abstraction. 2019-07-09 02:44:03 +00:00
whitequark 7b4fbf8e01 build.{dsl,res}: allow platform-dependent attributes using callables. 
Fixes #132.
 2019-07-08 11:15:04 +00:00
whitequark 0ab0a74ec1 hdl.rec: respect modifications to signals in Record.like(). 
Fixes #126.
 2019-07-08 10:59:15 +00:00
whitequark bfbeca4584 back.rtlil: don't name-prefix signals connected to instance ports. 
This gives particularly pathological results on IO buffers, like:
  connect \D_OUT_0 \user_led_0_user_led_0__o

Since subfragment signals are name-prefixed because this works well
for signals propagated upwards across hierarchy, this is never
desirable for instances.
 2019-07-08 10:48:07 +00:00
whitequark 0b844da4cf build.{dsl,res}: allow removing attributes from subsignals. 
This is useful when most attributes in a large composite resource
are the same, but a few signals are different, and also when building
abstractions around resources.

Fixes #128.
 2019-07-08 10:42:10 +00:00
whitequark f0c1c2cfeb build.dsl: allow assertions on subsignal widths. 
This is useful when building abstractions around resources where
the pin names are user-specified.

Fixes #129.
 2019-07-08 10:42:06 +00:00
whitequark a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. 
Fixes #125.
 2019-07-08 10:26:49 +00:00
whitequark 5c63177fc2 test: generate examples to verilog as part of unit tests. 
This is to make sure 806a62c2 doesn't happen again.
 2019-07-08 10:12:26 +00:00
whitequark 447bfa6ad5 compat.genlib.fsm: fix after commit dac62754. 2019-07-08 10:12:26 +00:00
whitequark ec7fcd3697 hdl.xfrm: don't overwrite source locations on ClockDomain signals. 
On the sample of examples/basic/*.py, there are no remaining
incorrectly inferred locations.
 2019-07-08 09:58:12 +00:00
whitequark 8c9fdf907f hdl.{dsl,mem,xfrm}: inject appropriate source locations. 
This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.

On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.
 2019-07-08 09:58:12 +00:00
whitequark 710a8d0bc1 back.rtlil: ignore empty source locations. 
This was a bug introduced during refactoring in 2492f490.
 2019-07-08 09:58:12 +00:00
whitequark dac6275493 hdl.ast: use keyword-only arguments as appropriate. 
As a motivation/related refactor, make sure each AST node exposes
src_loc_at in the constructor.
 2019-07-08 09:58:12 +00:00
whitequark 70f3563b5f back.rtlil: attach source locations to switches, not processes. 
This effectively reverts and reimplements half of commit 82903e49.
I was confused and did not realize that RTLIL does, in fact, have
attributes on switches.

After this commit, processes no longer have any source locations.
This is semantically fine, as the processes we emit are purely
artificial (because of LHS grouping), but I have not checked how
downstream tooling handles this.
 2019-07-08 09:10:09 +00:00
whitequark 2492f490f5 back.rtlil: use a more principled approach to attributes. NFC. 
This also refactors the RTLIL builder to use a more aspect-oriented
approach.
 2019-07-08 09:10:09 +00:00
Alain Péteut 31c54d32ef vendor.xilinx_7series: generate also binary bitfile. 
Fixes #139.
 2019-07-07 21:36:32 +00:00
William D. Jones b404d603fb vendor.xilinx_spartan_3_6: Add Spartan3A family support. 2019-07-07 20:44:48 +00:00
whitequark cb02a452e9 vendor.lattice_ecp5: don't leave LUT inputs disconnected. 
This causes YosysHQ/nextpnr#301.

Fixes #136.
 2019-07-07 02:34:22 +00:00
whitequark da1f58b7ae hdl.dsl: further clarify error message for incorrect nesting. 
Fixes #133.
 2019-07-07 01:03:59 +00:00
whitequark cb8be4a1b0 hdl.dsl: clarify error message for incorrect nesting. 
Refs #133.
 2019-07-07 00:59:57 +00:00
whitequark 3388b5b085 hdl.dsl: gracefully handle FSM with no states. 2019-07-07 00:59:34 +00:00
whitequark 146f3cb684 build.plat: source a script with toolchain environment. 
Fixes #131.
 2019-07-07 00:44:28 +00:00
whitequark 744154ebb5 build.run: only use os.path on the target OS. 
Before this commit, BuildPlan.add_file would use os.path.normpath,
which would be the wrong thing for cross-builds.
 2019-07-07 00:18:56 +00:00
whitequark ba64eb2037 build.run: make BuildProducts abstract, add LocalBuildProducts. 
This makes it clear that we plan to have remote builds as well.

Also, document everything in build.run.
 2019-07-07 00:09:07 +00:00
whitequark 1ee21d2007 build.plat, vendor.*: don't join strings passed as _opts overrides. 
Right now an array is expected in any _opts overrides, and if it is
actually a string (because it is passed via an environment variable,
usually), awkwardness results as each character is joined with ` `.

Fixes #130.
 2019-07-06 23:09:46 +00:00
whitequark b6b9f0fc21 build.run: make sure BuildProducts._root is not easily accessible. 2019-07-06 18:52:48 +00:00
Staf Verhaegen 2829d04033 vendor.xilinx_{7series,spartan6}: Support extra VHDL files. 2019-07-04 21:13:33 +00:00
whitequark 2e4cc47fcb hdl.dsl: fix src_loc_at for FSM state signal. 2019-07-03 16:34:31 +00:00
whitequark 82903e493a back.rtlil: emit \src attributes for processes via Switch and Assign. 
The locations are unfortunately not very precise, but they provide
some improvement over status quo.
 2019-07-03 16:27:54 +00:00
whitequark e351e27206 hdl.ast: fix src_loc_at for Mux(). 2019-07-03 15:25:14 +00:00
whitequark b471e33d7f build.res: detect physical conflicts earlier. 
This is useful for two reasons:
  1. nMigen can provide better error messages than the platform and
     do it earlier in the build pipeline.
  2. Many platforms handle diffpairs by only constraining the P pin;
     the N pin is completely ignored. If this is undetected,
     downstream users (human or software) can rely on this
     information assuming it is correct and introduce more errors.
     (Of course, this will not catch every mistake, but the most
     common is a copy-paste issue, and that will handle it.)

Fixes #124.
 2019-07-03 15:07:44 +00:00
whitequark 7059cb4931 hdl.rec: thread src_loc_at to all inner Signals and Records. 2019-07-03 14:49:20 +00:00
whitequark 33f21628bb vendor: give names to IO buffer instances. 
Fixes #123.
 2019-07-03 14:43:03 +00:00
whitequark 5800f00776 hdl.rec: accept Record(src_loc_at=...). 2019-07-03 14:35:48 +00:00
whitequark 668ff40a75 compat.fhdl.specials: mark CompatMemory as Elaboratable. 
This suppresses a warning that is not useful in the compat context.
 2019-07-03 13:28:57 +00:00
whitequark eeb6aca93d compat.fhdl.specials: use "sync" as default domain, not "sys". 
In compat.fhdl.module, we already default to "sync" as the default
clocked domain. Using "sys" in memories only would be inconsistent
and result in more bugs.
 2019-07-03 13:25:12 +00:00
whitequark c98b8f7c07 compat.fhdl.specials: fix Memory.get_port() after 94e8f479. 
This also makes sure the native ports are instantiated for correct
clock domain.
 2019-07-03 13:24:00 +00:00
whitequark 9eb81609d6 compat.fhdl.structure: fix If/Elif/Else after 32446831. 2019-07-03 13:19:15 +00:00
Sebastien Bourdeauducq 9a1048af50 lattice_ecp5: fix get_input 2019-07-03 10:25:32 +08:00
whitequark 0ab215e5ed hdl.ast: recognize a Enum used as decoder and format it better. 2019-07-02 19:34:44 +00:00
whitequark 7cc0b8cbf0 hdl.mem: fix naming of registers inside unnamed memories. 
Before this commit, `None` would leak into the vcd file with pysim.
 2019-07-02 18:45:35 +00:00
Alain Péteut 20553b1478 build.plat: add iter_extra_files method. 
* vendor.*: employ iter_extra_files.
 2019-07-02 18:25:29 +00:00
whitequark ea25806971 back.rtlil: emit \sig$next wires instead of \$next\sig. NFC. 
Just a bit more readable.
 2019-07-02 18:06:50 +00:00
whitequark dd5e513e42 back.rtlil: do not emit $next wires for comb signals. 
According to RTLIL semantics (that was undocumented before today),
the only purpose of `sync always` is to enable inference of latches,
because there is no other way to express them in terms of RTLIL
processes without ending up with a combinatorial loop. But, nMigen
specifically avoids latches, so this is not necessary.

This change results in major improvements in Verilog readability.

See also #98.
 2019-07-02 18:05:34 +00:00
whitequark 6b843b5be6 hdl.rec: implement slicing by component names. 
Fixes #121.
 2019-07-02 17:46:53 +00:00
whitequark 34f110100a hdl.rec: implement Record.like. 
Fixes #120.
 2019-07-02 17:46:53 +00:00
Alain Péteut b67f5cfa65 vendor.xilinx_7series: read extra .xdc files. 2019-07-02 08:23:37 +00:00