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Author SHA1 Message Date
Catherine 80343d1c4c hdl.ast: warn on fencepost error in Signal(range(x), reset=x). 
Also, relax the language reference inset from "warning" to "note"
since this is no longer something developers have to keep in mind
explicitly.
 2023-03-13 20:38:41 +00:00
Catherine ae1aeff0f2 lib.data: at most one Union field can have annotation with a default. 2023-03-04 09:34:50 +00:00
Catherine 16be75e02c lib.data: fix typo. 2023-03-03 09:03:53 +00:00
Catherine 0c4fda92fe hdl.ast: accept any constant-castable expression in Signal(reset=). 
See amaranth-lang/rfcs#4.

This functionality was not explicitly specified in the RFC but it
falls under "anywhere an integer or an enumeration is accepted".
 2023-03-03 06:22:56 +00:00
Catherine f77a335abf lib.enum: change shape mismatch warning category to SyntaxWarning. 2023-03-03 06:14:53 +00:00
Catherine c1b9c64e10 lib.data: ignore Python typing annotations in aggregate base class. 2023-03-03 03:45:12 +00:00
Catherine 14e73a73de hdl.ast: do not cast comparand to shape in Shape.__eq__. 
This doesn't match how other Python comparison operators work.
E.g. `1 == int("1")` but `1 != "1"`.
 2023-02-28 15:52:50 +00:00
Catherine 35561ea11a lib.data: improve reset value handling for Union. 
* Reject union initialization with more than one reset value.
* Replace the reset value specified in the class definition with
  the one provided during initalization instead of merging.
 2023-02-28 15:38:20 +00:00
Catherine c7ef05c894 lib.data: improve annotation handling for Struct and Union. 
* Annotations like `s: unsigned(4) = 1` are recognized and
  the assigned value is used as the reset value for the implicitly
  created `Signal`.
* Base classes inheriting from `Struct` and `Union` without
  specifying a layout are recognized.
* Classes that both inherit from a base class with a layout and
  specify a layout are rejected.
 2023-02-28 15:38:18 +00:00
Catherine 0ee5de036c hdl.ast: deprecate Sample, Past, Rose, Fell, Stable. 
See #526.
 2023-02-28 14:30:04 +00:00
Catherine 57612f1dce lib.enum: add Enum wrappers that allow specifying shape. 
See #756 and amaranth-lang/rfcs#3.
 2023-02-28 13:00:41 +00:00
Catherine ef2e9fa809 hdl.ast: Value.matches() with no arguments should return C(1). 
The behavior of the following must be always the same:
- `with m.Switch(v): with m.Case(*pats):`
- `with m.If(v.matches(*pats)):`
 2023-02-28 09:09:27 +00:00
Catherine 58721ee4fe hdl: implement constant-castable expressions. 
See #755 and amaranth-lang/rfcs#4.
 2023-02-27 22:38:38 +00:00
Catherine bef2052c1e hdl.ast: implement Value.__pos__. 2023-02-27 22:31:17 +00:00
Catherine fcc4f54367 lib.data: make Field() immutable. 
Mutability of Field isn't specified by the RFC and can cause issues
if the objects stored in Layout subclasses are mutated. There isn't
any reason to do that (the subclasses themselves are mutable and
handle that correctly), so disallow it.
 2023-02-21 17:58:28 +00:00
Catherine 7e3e10e733 lib.data: implement RFC 1 "Aggregate data structure library". 
See amaranth-lang/rfcs#1.
 2023-02-15 10:10:01 +00:00
Catherine 5a79c351e3 Remove features deprecated in version 0.3. 2023-01-31 21:38:27 +00:00
Catherine 7044e09110 hdl.ast: remove Shape<>tuple comparisons. 
See #691.

I missed this in commit 29502442.
 2023-01-31 15:23:06 +00:00
Catherine 29502442fb hdl.ast: remove Shape<>tuple casts. 
Closes #691.
 2023-01-31 12:58:29 +00:00
Arusekk de6b69370f hdl.ast: Do not warn on int Enums in Cat. 
This aligns with the behavior for plain Enums.
 2023-01-22 23:40:39 +00:00
Arusekk 58a0c68279 hdl.ast: allow typed int enums in Value.cast. 2023-01-22 23:40:39 +00:00
Catherine da26f1c915 hdl,back,sim: accept .as_signed() and .as_unsigned() on LHS. 
These operators are ignored when they are encountered on LHS, as
the signedness of the assignment target does not matter in Amaranth.
.as_signed() appears on LHS of assigns to signed aggregate fields.
 2022-09-24 07:19:47 +00:00
Catherine bf16acf2f0 hdl.ast: implement ShapeCastable (like ValueCastable). 
Refs #693.
 2022-09-24 07:19:03 +00:00
Catherine 0723f6bac9 hdl.ast: recursively cast ValueCastable objects to values. 2022-09-24 07:18:57 +00:00
Bastian Löher 02364a4fd7 sim: Fix clock phase in add_clock having to be specified in ps. 2022-02-04 16:46:52 +00:00
Irides 538c14116c sim.pysim: use "bench" as a top level root for testbench signals. 
Fixes #561.
 2021-12-16 15:46:05 +00:00
Catherine 847e46927b back.{verilog,rtlil}: fix commit d83c4a1b. 
The `ports` argument has been passed implicitly, via `**kwargs`, and
that was broken during the deprecation.

Closes #659.
 2021-12-14 10:47:04 +00:00
Irides d83c4a1b21 back.{rtlil,verilog}: deprecate implicit ports. 
Fixes #630.
 2021-12-13 12:21:44 +00:00
modwizcode 1ee2482c6b sim: represent time internally as 1ps units 
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.

Fixes #535.
 2021-12-13 08:15:11 +00:00
whitequark 7c161957bf build.dsl: check type of resource number. 
Fixes #599.
 2021-12-11 13:37:15 +00:00
whitequark 7e2b72826f sim.core: warn when driving a clock domain not in the simulation. 
Closes #566.
 2021-12-11 13:22:24 +00:00
whitequark ac13a5b3c9 sim._pyrtl: reject very large values. 
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
 2021-12-11 13:00:46 +00:00
whitequark 599615ee3a hdl.ir: reject elaboratables that elaborate to themselves. 
Fixes #592.
 2021-12-11 12:40:05 +00:00
whitequark 66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names. 
Closes #595.
 2021-12-11 11:12:25 +00:00
whitequark b452e0e871 hdl.ast: support division and modulo with negative divisor. 
Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
 2021-12-11 10:25:48 +00:00
whitequark 44b8bd29af hdl.ast: warn on bare integer value used in Cat()/Repl(). 
Fixes #639.
 2021-12-11 08:18:33 +00:00
whitequark de7c9acb19 _utils: don't crash trying to flatten() strings. 
Fixes #614.
 2021-12-11 07:39:35 +00:00
whitequark 909a3b8be7 Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
whitequark 11914a1e67 hdl.ast: improve interaction of ValueCastable with custom __getattr__. 
Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.
 2021-10-03 20:28:07 +00:00
whitequark e88d283ed3 hdl.ast: simplify Mux implementation. 2021-10-02 14:18:02 +00:00
whitequark 65499d5c45 hdl.ast: add tests for casting bare integers in {Cat,Repl}. 2021-10-02 13:18:11 +00:00
Robin Ole Heinemann b38b2cdad7 test.test_hdl_ast.OperatorTestCase: remove duplicate test_bool 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 2d85f888d6 tests: rename tests with duplicate names 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann b93a54ac58 tests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 25caf4045b *: remove unused imports 2021-05-18 20:18:55 +00:00
Thomas Watson d09dedfb48 tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements 2021-05-11 02:41:32 +00:00
Thomas Watson 7443f89200 hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements 2021-05-11 02:41:32 +00:00
whitequark c30dcea24d hdl.ast: handle int subclasses as slice start/stop values. 
Fixes #601.
 2021-03-18 23:52:23 +00:00
Robin Ole Heinemann 9af8201727 lib.fifo.AsyncFIFOBuffered: fix output register accounting 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann 2a7a3aef87 lib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency 2021-01-06 01:05:46 +00:00