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Author SHA1 Message Date
whitequark bfbeca4584 back.rtlil: don't name-prefix signals connected to instance ports. 
This gives particularly pathological results on IO buffers, like:
  connect \D_OUT_0 \user_led_0_user_led_0__o

Since subfragment signals are name-prefixed because this works well
for signals propagated upwards across hierarchy, this is never
desirable for instances.
 2019-07-08 10:48:07 +00:00
whitequark 710a8d0bc1 back.rtlil: ignore empty source locations. 
This was a bug introduced during refactoring in 2492f490.
 2019-07-08 09:58:12 +00:00
whitequark 70f3563b5f back.rtlil: attach source locations to switches, not processes. 
This effectively reverts and reimplements half of commit 82903e49.
I was confused and did not realize that RTLIL does, in fact, have
attributes on switches.

After this commit, processes no longer have any source locations.
This is semantically fine, as the processes we emit are purely
artificial (because of LHS grouping), but I have not checked how
downstream tooling handles this.
 2019-07-08 09:10:09 +00:00
whitequark 2492f490f5 back.rtlil: use a more principled approach to attributes. NFC. 
This also refactors the RTLIL builder to use a more aspect-oriented
approach.
 2019-07-08 09:10:09 +00:00
whitequark 82903e493a back.rtlil: emit \src attributes for processes via Switch and Assign. 
The locations are unfortunately not very precise, but they provide
some improvement over status quo.
 2019-07-03 16:27:54 +00:00
whitequark ea25806971 back.rtlil: emit \sig$next wires instead of \$next\sig. NFC. 
Just a bit more readable.
 2019-07-02 18:06:50 +00:00
whitequark dd5e513e42 back.rtlil: do not emit $next wires for comb signals. 
According to RTLIL semantics (that was undocumented before today),
the only purpose of `sync always` is to enable inference of latches,
because there is no other way to express them in terms of RTLIL
processes without ending up with a combinatorial loop. But, nMigen
specifically avoids latches, so this is not necessary.

This change results in major improvements in Verilog readability.

See also #98.
 2019-07-02 18:05:34 +00:00
whitequark f75a0163f9 back.rtlil: fix Array regression in 32446831. 
Fixes #117.
 2019-07-01 01:53:56 +00:00
whitequark 9c54d0c061 back.pysim: create unique ResetSynchronizer internal domains. 
Commit 300d47ca introduced the same bug commit 779f3ee9 was trying to
avoid, but now only in the simulator. Since the names in simulator
don't have to make any sense, just use DUID to generate them.
 2019-06-28 08:34:43 +00:00
whitequark 300d47ca2e back.pysim: override ResetSynchronizer implementation. 
This was rewritten to use Yosys cells in 779f3ee9 to avoid leaking
the interior clock domain, but the simulator doesn't understand Yosys
cells. So, use the old implementation in the simulator.
 2019-06-28 07:49:14 +00:00
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
 2019-06-28 04:37:08 +00:00
whitequark 48d4ee4031 hdl.ir, back.rtlil: allow specifying attributes on instances. 
Fixes #107.
 2019-06-28 04:14:38 +00:00
whitequark 6f4e3156d8 back.pysim: fix scope screwup. 2019-06-26 05:22:09 +00:00
whitequark e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. 
This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase
 2019-06-25 22:01:14 +00:00
whitequark 066dd799e8 back.pysim: check for a clock being added twice. 
This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.
 2019-06-11 03:54:22 +00:00
whitequark d2d8c2b8bf back.rtlil: mask memory init values. 
This handles both init values that are too wide, which happens if
their magnitude is too high, or if they're negative.

Fixes #96.
 2019-06-11 03:43:09 +00:00
whitequark f17375a60b back.rtlil: allow specifying platform for convert(). 2019-05-26 17:10:56 +00:00
whitequark 921f506e69 back.rtlil: assign undriven signals to their reset value. 
Fixes #35.
 2019-05-13 08:33:55 +00:00
whitequark 97af266645 back.verilog: allow stripping the src attribute, for cleaner output. 2019-04-22 14:59:53 +00:00
whitequark 585514e6ed hdl.ir: rework named port handling for Instances. 
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
 2019-04-22 07:46:47 +00:00
whitequark 85ae99c1b4 back.rtlil: emit nmigen.hierarchy attribute. 
Fixes #54.
 2019-04-21 07:55:08 +00:00
whitequark 083016d747 back.rtlil: only expand legalized values in Array/Part context on RHS. 
Otherwise the following code fails to compile:

    index = Signal(1)
    array = Array(range(2))
    with m.If(0 == array[index]):
        m.d.sync += index.eq(0)

Fixes #51.
 2019-04-21 06:43:31 +00:00
whitequark f22106e5ef back.rtlil: allow record slices on LHS. 2019-04-20 08:12:29 +00:00
whitequark a57c72d606 back.rtlil: fix off-by-one in Part legalization. 
Fixes #52.
 2019-03-28 05:12:12 +00:00
whitequark 43e4833ddb back.rtlil: accept ast.Const as cell parameter. 2019-01-26 23:25:54 +00:00
whitequark e74dbc3377 back.pysim: support async reset. 2019-01-26 18:07:43 +00:00
whitequark 8686e9aa06 back.pysim: give better names to unnamed fragments and their signals. 
Was: top.#0, top.None_clk
Now: top.U0, top.U0_clk

(U for Unnamed, or similarly, an unit refdes.)
 2019-01-26 18:07:16 +00:00
whitequark b133eb735f back.rtlil: accept any elaboratable, not just fragments. 2019-01-26 16:11:29 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark 7b25665fde back.pysim: fix behavior of initial cycle for sync processes. 
The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.
 2019-01-25 20:37:56 +00:00
whitequark 12e04e4ee5 back.pysim: wake up processes before ever committing any values. 
Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
 2019-01-21 16:00:25 +00:00
whitequark b50b47d984 hdl.ast: give Assert and Assume their own src_loc. 
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
 2019-01-19 00:08:51 +00:00
whitequark 66466a8a0e back.rtlil: only emit each AnyConst/AnySeq cell once. 
These are semantically like signals, not like constants.
 2019-01-18 01:34:48 +00:00
whitequark 198efcad31 hdl.xfrm: add SampleLowerer. 2019-01-17 01:41:02 +00:00
whitequark f2425001aa back.rtlil: slightly nicer naming for $next signals. NFC. 2019-01-16 17:20:38 +00:00
whitequark 935bf2d8cf back.rtlil: rename \sig$next to $next$sig. 
These used to serve a useful purpose being public, back when the RTLIL
backend was immature. Not anymore; now they merely clutter up views
in gtkwave and so on.
 2019-01-16 14:51:20 +00:00
whitequark 6191760c30 Unbreak 655d02d5. 2019-01-15 23:09:10 +00:00
William D. Jones 655d02d5b8 back.rtlil: Generate $anyconst and $anyseq cells. 2019-01-15 22:52:45 +00:00
William D. Jones 77728c2dea hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children. 2019-01-15 22:52:45 +00:00
whitequark cbf7bd6e31 back.pysim: handle non-driven, non-port signals. 
Fixes #20.
 2019-01-13 08:31:38 +00:00
whitequark 06faeee357 back.verilog: better error message if Yosys is not found. 
Fixes #17.
 2019-01-13 08:10:23 +00:00
whitequark 307de722cb back.verilog: remove undriven check. 
This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.

Fixes #23.
 2019-01-08 22:43:09 +00:00
Adam Greig 560bb007cc Give the top level scope a name to fix VCD hierarchy. 2019-01-06 00:10:37 +00:00
whitequark ef1e0b8d55 back.rtlil: translate empty slices correctly. 2019-01-02 18:14:29 +00:00
William D. Jones f31055a4ef back.rtlil: Generate RTLIL for Assert/Assume statements. 2019-01-02 11:17:39 +00:00
William D. Jones f77dc40256 hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children. 2019-01-02 11:17:39 +00:00
whitequark 1a9dcd2f28 back.rtlil: fix typo. 2019-01-01 08:50:28 +00:00
whitequark ae3c5834ed back.rtlil: match shape of Array elements to ArrayProxy shape. 
Fixes #15.
 2018-12-31 03:43:34 +00:00
whitequark cdc40eaa9b back.rtlil: fix typo. 2018-12-31 03:37:38 +00:00
whitequark 849c649259 back.pysim: warn if simulation is not run. 
This would have prevented 3ea35b85.
 2018-12-29 15:02:04 +00:00
whitequark 92a96e1644 hdl.rec: add basic record support. 2018-12-28 13:22:10 +00:00
whitequark fe8cb55204 lib.cdc: add tests for MultiReg. 2018-12-26 12:58:30 +00:00
whitequark b4fbef65ca back.rtlil: clarify $verilog_initial_trigger behavior. NFC. 2018-12-26 06:45:57 +00:00
whitequark 010ddb96b5 back.rtlil: unbreak d47c1f8a. 2018-12-24 19:11:07 +00:00
whitequark d47c1f8a8a back.rtlil: use one $meminit cell, not one per word. 
This is *far* more efficient.
 2018-12-24 11:53:58 +00:00
whitequark 98f554aa08 hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. 
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
 2018-12-24 02:17:28 +00:00
whitequark 1c7c75a254 hdl.xfrm: implement SwitchCleaner, for pruning empty switches. 2018-12-24 02:02:59 +00:00
whitequark fc0fb9d89f back.rtlil: always output negative values as two's complement. 
- is valid in RTLIL but means something entirely different.
 2018-12-24 01:38:32 +00:00
whitequark 5702767263 back.rtlil: emit dummy logic to work around Verilog deficiencies. 2018-12-23 10:14:42 +00:00
whitequark 9faa1d3742 back.rtlil: do not translate empty fragments. 
The resulting Verilog confuses some frontends.
 2018-12-23 09:20:02 +00:00
whitequark 45a474788c back.rtlil: only translate switch tests once. 
This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
 2018-12-23 07:17:52 +00:00
whitequark 2b6ddbb713 back.rtlil: fix swapped operands in mux codegen. 2018-12-23 06:47:38 +00:00
whitequark 59c7540aeb back.rtlil: split processes as finely as possible. 
This makes simulation work correctly (by introducing delta cycles,
and therefore, making the overall Verilog simulation deterministic)
at the price of pessimizing mux trees generated by Yosys and Synplify
frontends, sometimes severely.
 2018-12-22 10:03:16 +00:00
whitequark d29929912f back.rtlil: remove useless condition. NFC. 2018-12-22 07:24:15 +00:00
whitequark 98a9744be4 hdl.xfrm: Abstract*Transformer→*Visitor 2018-12-22 06:03:39 +00:00
whitequark 37b81309d3 back.rtlil: always initialize the entire memory. 
This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.
 2018-12-22 05:27:42 +00:00
whitequark 6ee80408bb back.verilog: do not rename internal signals. 
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
 2018-12-22 00:53:40 +00:00
whitequark 48d13e47ec back.pysim: handle out of bounds ArrayProxy indexes. 2018-12-21 12:32:08 +00:00
whitequark 7ae7683fed back.pysim: give numeric names to unnamed subfragments in VCD. 2018-12-21 12:29:33 +00:00
whitequark a40e2cac4b back.pysim: fix an issue with too few funclet slots. 2018-12-21 10:25:28 +00:00
whitequark a061bfaa6c hdl.mem: tie rdport.en high for asynchronous or transparent ports. 2018-12-21 04:22:16 +00:00
whitequark 8d58cbf230 back.rtlil: more consistent prefixing for subfragment port wires. 2018-12-21 04:21:11 +00:00
whitequark 2b4a8510ca back.rtlil: implement memories. 2018-12-21 01:55:59 +00:00
whitequark 6672ab2e3f back.rtlil: explicitly pad constants with zeroes. 
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
 2018-12-21 01:51:18 +00:00
whitequark 221f108fbe back.rtlil: fix translation of Cat. 2018-12-21 01:48:02 +00:00
whitequark f7fec804ec ir: allow non-Signals in Instance ports. 2018-12-20 23:40:40 +00:00
whitequark dbbcc49a71 hdl.ast: Cat.{operands→parts} 2018-12-18 19:15:50 +00:00
whitequark 4199674edd back.pysim: implement *. 2018-12-18 18:02:21 +00:00
whitequark 07e9cfa939 test.sim: add tests for sync functionality and errors. 2018-12-18 17:53:50 +00:00
whitequark 7fa82a70be back.pysim: eliminate most dictionary lookups. 
This makes the Glasgow testsuite about 30% faster.
 2018-12-18 16:36:54 +00:00
whitequark c5f169988b back.pysim: use arrays instead of dicts for signal values. 
This makes the Glasgow testsuite about 40% faster.
 2018-12-18 05:20:20 +00:00
whitequark 39605ef551 back.pysim: naming. NFC. 2018-12-18 04:46:36 +00:00
whitequark 65702719e8 back.pysim: fix an off-by-1 in add_sync_process(). 2018-12-18 04:43:04 +00:00
whitequark 34b81d0b87 back.pysim: trigger processes waiting on Tick() exactly at clock edge. 2018-12-18 04:37:39 +00:00
whitequark d6e98fd934 back.pysim: continue running simulator processes until they suspend. 2018-12-18 03:05:16 +00:00
whitequark c7f9386eab fhdl.ir: add black-box fragments, fragment parameters, and Instance. 2018-12-17 22:55:39 +00:00
whitequark 8d1639a5a8 hdl, back: add and use SignalSet/SignalDict. 2018-12-17 17:21:29 +00:00
whitequark f1e390cbc9 back.rtlil: update for Yosys master. 2018-12-17 15:50:43 +00:00
whitequark 850674637a back.rtlil: implement Array. 2018-12-17 01:15:23 +00:00
whitequark 87cd045ac3 back.rtlil: implement Part. 2018-12-17 01:05:08 +00:00
whitequark f968678937 back.rtlil: handle reset_less domains. 2018-12-16 23:52:47 +00:00
whitequark 91b7561a00 back.rtlil: extract _StatementCompiler. NFC. 2018-12-16 22:26:58 +00:00
whitequark b9a0af8bde back.rtlil: simplify. NFC. 2018-12-16 21:00:00 +00:00
whitequark 635094350f back.rtlil: properly escape strings in attributes. 2018-12-16 20:27:36 +00:00
whitequark 33f32a25f5 back.rtlil: prepare for Yosys sigspec slicing improvements. 
See YosysHQ/yosys#741.
 2018-12-16 18:03:14 +00:00
whitequark 9bce35098f back.rtlil: avoid illegal slices. 
Not sure what to do with {} [] on LHS yet--fix Yosys?
 2018-12-16 17:41:11 +00:00
whitequark e86104d3a6 back.rtlil: use slicing to match shape when reducing width. 2018-12-16 16:20:45 +00:00
whitequark 2833b36c73 back.rtlil: don't emit a slice if all bits are used. 2018-12-16 16:05:38 +00:00
whitequark 9794e732e2 back.rtlil: reorganize value compiler into LHS/RHS. 
This also implements Cat on LHS.
 2018-12-16 13:33:34 +00:00
whitequark ed39748889 back.rtlil: fix naming. NFC. 2018-12-16 11:26:31 +00:00