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Author SHA1 Message Date
whitequark 97b990272e lib.fifo: formally verify FIFO contract. 2019-01-19 00:52:56 +00:00
whitequark b50b47d984 hdl.ast: give Assert and Assume their own src_loc. 
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
 2019-01-19 00:08:51 +00:00
whitequark 66466a8a0e back.rtlil: only emit each AnyConst/AnySeq cell once. 
These are semantically like signals, not like constants.
 2019-01-18 01:34:48 +00:00
Alain Péteut 60089db075 cli: add missing default for generate 2019-01-17 20:45:07 +00:00
whitequark 5a831ce31c lib.fifo: add basic formal specification. 2019-01-17 05:40:25 +00:00
whitequark fa8e876356 hdl.ast: allow sampling ClockSignal, ResetSignal. 2019-01-17 05:23:06 +00:00
whitequark 8c96675580 hdl.ast: add Past, Stable, Rose, Fell. 2019-01-17 04:31:27 +00:00
whitequark 16f90d3585 formal: extract from toplevel module. 
The nMigen formal language is about to get *much* larger and will
keep growing faster than the rest of nMigen language, so it makes
good sense to extract it. Further, this makes it easier to qualify
formal keywords like `formal.AnyConst()` without directly importing
hdl.ast.
 2019-01-17 01:43:07 +00:00
whitequark 198efcad31 hdl.xfrm: add SampleLowerer. 2019-01-17 01:41:02 +00:00
whitequark b3de114d67 hdl.ast: add Sample. 2019-01-17 01:36:27 +00:00
whitequark b78a2be9f6 lib.fifo: port sync FIFO queues from Migen. 2019-01-16 17:20:38 +00:00
whitequark cb2f18ee37 hdl.ast: fix naming of Signal.like() signals when tracer fails. 2019-01-16 17:20:38 +00:00
whitequark f2425001aa back.rtlil: slightly nicer naming for $next signals. NFC. 2019-01-16 17:20:38 +00:00
whitequark 935bf2d8cf back.rtlil: rename \sig$next to $next$sig. 
These used to serve a useful purpose being public, back when the RTLIL
backend was immature. Not anymore; now they merely clutter up views
in gtkwave and so on.
 2019-01-16 14:51:20 +00:00
whitequark 6191760c30 Unbreak 655d02d5. 2019-01-15 23:09:10 +00:00
William D. Jones 655d02d5b8 back.rtlil: Generate $anyconst and $anyseq cells. 2019-01-15 22:52:45 +00:00
William D. Jones 77728c2dea hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children. 2019-01-15 22:52:45 +00:00
William D. Jones 6fdbc3d885 hdl.ast: Add AnyConst and AnySeq value types. 2019-01-15 22:52:45 +00:00
whitequark c4276f7cf7 lib.io: pass pin to platform.get_tristate(). 2019-01-14 21:39:19 +00:00
whitequark b534e92dd5 hdl.ir: allow explicitly requesting flattening. 2019-01-14 17:04:23 +00:00
whitequark 6f66885c09 lib.io: lower to platform-independent tristate buffer. 2019-01-14 16:50:04 +00:00
whitequark 011bf2258e hdl: make ClockSignal and ResetSignal usable on LHS. 
Fixes #8.
 2019-01-14 15:38:16 +00:00
whitequark 664b4bcb3a hdl.dsl: cases wider than switch test value are unreachable. 
In 3083c1d6 they were erroneously fixed via truncation.
 2019-01-13 08:51:49 +00:00
whitequark 3083c1d6dd hdl.dsl: accept (but warn on) cases wider than switch test value. 
Fixes #13.
 2019-01-13 08:46:28 +00:00
whitequark cbf7bd6e31 back.pysim: handle non-driven, non-port signals. 
Fixes #20.
 2019-01-13 08:31:38 +00:00
whitequark 06faeee357 back.verilog: better error message if Yosys is not found. 
Fixes #17.
 2019-01-13 08:10:23 +00:00
whitequark 307de722cb back.verilog: remove undriven check. 
This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.

Fixes #23.
 2019-01-08 22:43:09 +00:00
Adam Greig 560bb007cc Give the top level scope a name to fix VCD hierarchy. 2019-01-06 00:10:37 +00:00
whitequark a2b04d71d0 hdl.ast: allow slicing [n:n] into n-bit value. 2019-01-02 18:14:57 +00:00
whitequark ef1e0b8d55 back.rtlil: translate empty slices correctly. 2019-01-02 18:14:29 +00:00
William D. Jones f31055a4ef back.rtlil: Generate RTLIL for Assert/Assume statements. 2019-01-02 11:17:39 +00:00
William D. Jones f77dc40256 hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children. 2019-01-02 11:17:39 +00:00
William D. Jones 2412650f56 hdl.dsl: Support Assert and Assume where an Assign can occur. 2019-01-02 11:17:39 +00:00
William D. Jones e6517a33c7 hdl.ast: Add Assert and Assign statements. 2019-01-02 11:17:39 +00:00
whitequark ea7e19ed5c hdl.ast: experimentally add Value._as_const. 
Useful for writing e.g. decoders that accept Cat, etc as argument.
 2019-01-01 09:50:39 +00:00
whitequark 1a9dcd2f28 back.rtlil: fix typo. 2019-01-01 08:50:28 +00:00
whitequark 3c07d8d52c hdl.rec: include record name in error message. 2019-01-01 03:39:12 +00:00
whitequark 031a9e2616 hdl.rec: use a helpful error on unknown field reference. 2019-01-01 03:35:34 +00:00
whitequark d78e6c155b hdl.mem: add DummyPort, for testing and verification. 2019-01-01 03:08:10 +00:00
whitequark ae3c5834ed back.rtlil: match shape of Array elements to ArrayProxy shape. 
Fixes #15.
 2018-12-31 03:43:34 +00:00
whitequark cdc40eaa9b back.rtlil: fix typo. 2018-12-31 03:37:38 +00:00
whitequark 39eb2e8fa7 lib.cdc: fix tests to actually run. 2018-12-29 15:02:44 +00:00
whitequark 849c649259 back.pysim: warn if simulation is not run. 
This would have prevented 3ea35b85.
 2018-12-29 15:02:04 +00:00
whitequark 92a96e1644 hdl.rec: add basic record support. 2018-12-28 13:22:10 +00:00
whitequark d66bbb0df8 tracer: factor out get_src_loc(). 2018-12-28 01:31:24 +00:00
whitequark 3ea35b8566 lib.coding: fix tests to actually run, and fix code to fix tests. 2018-12-27 21:45:55 +00:00
whitequark 470d66934f hdl.dsl: add support for fsm.ongoing(). 2018-12-27 16:19:01 +00:00
whitequark de50ccec90 hdl.mem: add missing __all__. 2018-12-27 16:19:01 +00:00
Jean-François Nguyen 73ed870309 compat.genlib.coding: fix import. 2018-12-26 14:30:01 +00:00
whitequark 528747703d lib.coding: port from Migen. 2018-12-26 13:19:34 +00:00
whitequark fe8cb55204 lib.cdc: add tests for MultiReg. 2018-12-26 12:58:30 +00:00
whitequark 35a44f017f hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too. 2018-12-26 12:42:43 +00:00
whitequark 934546e633 hdl.dsl: provide generated values for FSMs. 2018-12-26 12:39:05 +00:00
whitequark 040811c2e5 hdl.ir: add an API for retrieving generated values, like FSM signal. 
This is useful for tests.
 2018-12-26 12:35:35 +00:00
whitequark 597d778cf6 examples: add an FSM usage example (UART receiver). 2018-12-26 10:10:27 +00:00
whitequark 72039b6072 hdl.dsl: add signal decoder to FSM state signal. 2018-12-26 09:45:12 +00:00
whitequark 54e3195dcb hdl.dsl: implement FSM. 2018-12-26 08:55:04 +00:00
whitequark b4fbef65ca back.rtlil: clarify $verilog_initial_trigger behavior. NFC. 2018-12-26 06:45:57 +00:00
whitequark 010ddb96b5 back.rtlil: unbreak d47c1f8a. 2018-12-24 19:11:07 +00:00
whitequark f05bd2a137 hdl.mem: allow omitting memory simulation logic. 
Trying to transform very large arrays is slow.
 2018-12-24 11:53:59 +00:00
whitequark d47c1f8a8a back.rtlil: use one $meminit cell, not one per word. 
This is *far* more efficient.
 2018-12-24 11:53:58 +00:00
whitequark 98f554aa08 hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. 
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
 2018-12-24 02:17:28 +00:00
whitequark 1c7c75a254 hdl.xfrm: implement SwitchCleaner, for pruning empty switches. 2018-12-24 02:02:59 +00:00
whitequark fc0fb9d89f back.rtlil: always output negative values as two's complement. 
- is valid in RTLIL but means something entirely different.
 2018-12-24 01:38:32 +00:00
whitequark 5702767263 back.rtlil: emit dummy logic to work around Verilog deficiencies. 2018-12-23 10:14:42 +00:00
whitequark 9faa1d3742 back.rtlil: do not translate empty fragments. 
The resulting Verilog confuses some frontends.
 2018-12-23 09:20:02 +00:00
whitequark 45a474788c back.rtlil: only translate switch tests once. 
This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
 2018-12-23 07:17:52 +00:00
whitequark 4e49772f67 cli: generate: guess file type from extension. 2018-12-23 07:13:17 +00:00
whitequark 2b6ddbb713 back.rtlil: fix swapped operands in mux codegen. 2018-12-23 06:47:38 +00:00
whitequark cf79738744 cli: new module, for basic design generaton/simulation. 2018-12-23 00:06:58 +00:00
whitequark 621dddebfd hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer. 2018-12-22 22:19:14 +00:00
whitequark 3448953f61 compat.genlib.fsm: fix naming for non-Signal LHS. 2018-12-22 22:00:58 +00:00
whitequark 68dae9f50e hdl.ir: flatten hierarchy based on memory accesses, too. 2018-12-22 21:43:46 +00:00
whitequark fd89d2fc9d hdl.ir: factor out _merge_subfragment. NFC. 2018-12-22 19:04:49 +00:00
whitequark 59c7540aeb back.rtlil: split processes as finely as possible. 
This makes simulation work correctly (by introducing delta cycles,
and therefore, making the overall Verilog simulation deterministic)
at the price of pessimizing mux trees generated by Yosys and Synplify
frontends, sometimes severely.
 2018-12-22 10:03:16 +00:00
whitequark d29929912f back.rtlil: remove useless condition. NFC. 2018-12-22 07:24:15 +00:00
whitequark ae0cb48fbb hdl.xfrm: implement LHSGroupAnalyzer. 2018-12-22 06:58:24 +00:00
whitequark 98a9744be4 hdl.xfrm: Abstract*Transformer→*Visitor 2018-12-22 06:03:39 +00:00
whitequark 37b81309d3 back.rtlil: always initialize the entire memory. 
This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.
 2018-12-22 05:27:42 +00:00
whitequark 99b778158d compat: use nicer names for next_value/next_value_ce signals. 2018-12-22 02:05:49 +00:00
whitequark 8730895d8c hdl.mem: allow changing init value after creating memory. 2018-12-22 01:09:03 +00:00
whitequark 6ee80408bb back.verilog: do not rename internal signals. 
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
 2018-12-22 00:53:40 +00:00
whitequark 5361b4c22b compat: fix confusing naming for memory port address signal. 2018-12-22 00:53:05 +00:00
whitequark f6772759c8 hdl.ir: fix port propagation between siblings, in the other direction. 2018-12-22 00:31:31 +00:00
whitequark 0df543b204 compat: do not finalize native submodules twice. 2018-12-22 00:02:31 +00:00
whitequark a4183eba69 hdl.mem: use more informative signal naming for ports. 2018-12-21 23:55:02 +00:00
whitequark 913339c04a hdl.ir: fix port propagation between siblings. 2018-12-21 23:53:18 +00:00
whitequark 00ef7a78d3 compat: provide verilog.convert shim. 2018-12-21 13:53:06 +00:00
whitequark fc7da1be2d hdl.ir: do not flatten instances or collect ports from their statements. 
This results in absurd behavior for memories.
 2018-12-21 13:52:18 +00:00
whitequark 568d3c5b7d compat: provide Memory shim. 2018-12-21 13:15:52 +00:00
whitequark fa2af27bb0 hdl.mem: ensure transparent read port model has correct latency. 2018-12-21 13:01:08 +00:00
whitequark 48d13e47ec back.pysim: handle out of bounds ArrayProxy indexes. 2018-12-21 12:32:08 +00:00
whitequark 7ae7683fed back.pysim: give numeric names to unnamed subfragments in VCD. 2018-12-21 12:29:33 +00:00
whitequark af7db882c0 hdl.mem: use different naming for array signals. 
It looks like [] is confusing gtkwave somehow.
 2018-12-21 12:26:49 +00:00
whitequark e58d9ec74d hdl.mem: add simulation model for memory. 2018-12-21 11:54:32 +00:00
whitequark a40e2cac4b back.pysim: fix an issue with too few funclet slots. 2018-12-21 10:25:28 +00:00
whitequark c49211c76a hdl.mem: add tests for all error conditions. 2018-12-21 06:07:16 +00:00
whitequark a061bfaa6c hdl.mem: tie rdport.en high for asynchronous or transparent ports. 2018-12-21 04:22:16 +00:00
whitequark 8d58cbf230 back.rtlil: more consistent prefixing for subfragment port wires. 2018-12-21 04:21:11 +00:00
whitequark b0bd7bfaca hdl.ir: correctly handle named output and inout ports. 2018-12-21 04:03:03 +00:00
whitequark 2b4a8510ca back.rtlil: implement memories. 2018-12-21 01:55:59 +00:00
whitequark 6d9a6b5d84 hdl.mem: implement memories. 2018-12-21 01:53:32 +00:00
whitequark 6672ab2e3f back.rtlil: explicitly pad constants with zeroes. 
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
 2018-12-21 01:51:18 +00:00
whitequark 221f108fbe back.rtlil: fix translation of Cat. 2018-12-21 01:48:02 +00:00
whitequark f7fec804ec ir: allow non-Signals in Instance ports. 2018-12-20 23:40:40 +00:00
whitequark 0f2c7e7161 compat: import genlib.record from Migen. 2018-12-18 20:04:22 +00:00
whitequark a90748303c compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices. 2018-12-18 20:03:32 +00:00
whitequark dbbcc49a71 hdl.ast: Cat.{operands→parts} 2018-12-18 19:15:50 +00:00
whitequark 4199674edd back.pysim: implement *. 2018-12-18 18:02:21 +00:00
whitequark 07e9cfa939 test.sim: add tests for sync functionality and errors. 2018-12-18 17:53:50 +00:00
whitequark 7fa82a70be back.pysim: eliminate most dictionary lookups. 
This makes the Glasgow testsuite about 30% faster.
 2018-12-18 16:36:54 +00:00
whitequark 7341d0d7ef hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim. 2018-12-18 16:13:29 +00:00
whitequark c5f169988b back.pysim: use arrays instead of dicts for signal values. 
This makes the Glasgow testsuite about 40% faster.
 2018-12-18 05:20:20 +00:00
whitequark 39605ef551 back.pysim: naming. NFC. 2018-12-18 04:46:36 +00:00
whitequark 65702719e8 back.pysim: fix an off-by-1 in add_sync_process(). 2018-12-18 04:43:04 +00:00
whitequark 34b81d0b87 back.pysim: trigger processes waiting on Tick() exactly at clock edge. 2018-12-18 04:37:39 +00:00
whitequark d6e98fd934 back.pysim: continue running simulator processes until they suspend. 2018-12-18 03:05:16 +00:00
whitequark c7f9386eab fhdl.ir: add black-box fragments, fragment parameters, and Instance. 2018-12-17 22:55:39 +00:00
whitequark 8d1639a5a8 hdl, back: add and use SignalSet/SignalDict. 2018-12-17 17:21:29 +00:00
whitequark 8c4de99c0d hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC. 2018-12-17 17:21:29 +00:00
whitequark f1e390cbc9 back.rtlil: update for Yosys master. 2018-12-17 15:50:43 +00:00
whitequark 850674637a back.rtlil: implement Array. 2018-12-17 01:15:23 +00:00
whitequark 87cd045ac3 back.rtlil: implement Part. 2018-12-17 01:05:08 +00:00
whitequark f968678937 back.rtlil: handle reset_less domains. 2018-12-16 23:52:47 +00:00
whitequark 015998eba9 hdl.dsl: add clock domain support. 2018-12-16 23:51:24 +00:00
whitequark b2f828387a hdl.dsl: cleanup. NFC. 2018-12-16 23:44:00 +00:00
whitequark 91b7561a00 back.rtlil: extract _StatementCompiler. NFC. 2018-12-16 22:26:58 +00:00
whitequark b9a0af8bde back.rtlil: simplify. NFC. 2018-12-16 21:00:00 +00:00
whitequark 635094350f back.rtlil: properly escape strings in attributes. 2018-12-16 20:27:36 +00:00
whitequark 33f32a25f5 back.rtlil: prepare for Yosys sigspec slicing improvements. 
See YosysHQ/yosys#741.
 2018-12-16 18:03:14 +00:00
whitequark db5fd1e4c4 compat.fhdl.structure: only convert to bool in If/Elif if necessary. 2018-12-16 17:41:42 +00:00
whitequark 9bce35098f back.rtlil: avoid illegal slices. 
Not sure what to do with {} [] on LHS yet--fix Yosys?
 2018-12-16 17:41:11 +00:00
whitequark e86104d3a6 back.rtlil: use slicing to match shape when reducing width. 2018-12-16 16:20:45 +00:00
whitequark 2833b36c73 back.rtlil: don't emit a slice if all bits are used. 2018-12-16 16:05:38 +00:00
whitequark 9794e732e2 back.rtlil: reorganize value compiler into LHS/RHS. 
This also implements Cat on LHS.
 2018-12-16 13:33:34 +00:00
whitequark ed39748889 back.rtlil: fix naming. NFC. 2018-12-16 11:26:31 +00:00
whitequark 2be76fda3c hdl.xfrm: separate AST traversal from AST identity mapping. 
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
 2018-12-16 11:25:52 +00:00
whitequark 286a8009c8 compat.fhdl: reexport Array. 2018-12-16 10:39:54 +00:00
whitequark d4e8d3e95a back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. 2018-12-16 10:31:42 +00:00
whitequark d9579219ee test.sim: generalize assertOperator. NFC. 2018-12-15 21:08:29 +00:00
whitequark bdb8db2826 back.pysim: add (stub) LHSValueCompiler. 2018-12-15 21:01:38 +00:00
whitequark 20a04bca88 back.pysim: implement Part. 2018-12-15 20:58:06 +00:00
whitequark 54fb999c99 back.pysim: implement ArrayProxy. 2018-12-15 19:37:36 +00:00
whitequark 80c5343600 hdl.ast: implement Array and ArrayProxy. 2018-12-15 17:16:31 +00:00
whitequark c6e7a93717 hdl: appropriately rename tests. NFC. 2018-12-15 16:13:53 +00:00
whitequark f603b735e8 hdl.ast: improve ClockSignal, ResetSignal documentation. 2018-12-15 14:58:31 +00:00
whitequark 790eb05a92 Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
whitequark b5a1efa0c8 Move star imports to make from nmigen import * usable. 2018-12-15 14:20:10 +00:00
whitequark 1f10bd96b9 Determine Migen's API surface and document compatibility summary. 
This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.
 2018-12-15 11:52:30 +00:00
whitequark b70340c0da pyback.sim: test Slice, Cat, Repl. 2018-12-15 10:09:14 +00:00
whitequark db4600d52b fhdl.ast, back.pysim: implement shifts. 2018-12-15 09:58:30 +00:00
whitequark 46f5addf05 fhdl.ast: refactor Operator.shape(). NFC. 2018-12-15 09:46:20 +00:00
whitequark 3a8685c352 Consistently use '{!r}' in and only in TypeError messages. 2018-12-15 09:31:58 +00:00
whitequark f9f7921959 fhdl.ir: test iter_comb(), iter_sync() and iter_signals(). 2018-12-15 09:26:36 +00:00
whitequark f5e8c9033d fhdl.ir: fix incorrect uses of positive to say non-negative. 
Also test Part and Slice properly.
 2018-12-15 09:26:23 +00:00
whitequark 9010805040 compat.fhdl.structure: handle If/Elif with multi-bit condition. 2018-12-15 00:10:54 +00:00
whitequark ecea721f43 compat.fhdl.module: allow adding native submodules to compat modules. 2018-12-14 23:56:50 +00:00
whitequark 1c7b43ea49 Fix deprecations in Python 3.7. 2018-12-14 23:56:50 +00:00
whitequark 7108111ad0 back.pysim: preserve process locations through add_sync_process(). 2018-12-14 23:27:36 +00:00
whitequark c4ba5a3915 fhdl.ast: clean up stub error messages. NFC. 2018-12-14 23:07:16 +00:00
whitequark 2001359b66 fhdl.ir: automatically flatten hierarchy to resolve driver conflicts. 
Fixes #5.
 2018-12-14 22:48:17 +00:00
whitequark 579feaba4e fhdl.ir: Fragment.{drive→add_driver} 2018-12-14 20:58:29 +00:00
whitequark 0015713bfb back.pysim: count delta cycles separately to avoid clock drift. 2018-12-14 20:52:41 +00:00
whitequark a6a8703a0e back.pysim: simplify. 2018-12-14 20:45:45 +00:00
whitequark 7e3cf26cf8 back.pysim: revert 70ebc6f2. 2018-12-14 19:46:08 +00:00
whitequark 71304c9fe7 back.pysim: fix implicit boolean conversion. 2018-12-14 19:08:06 +00:00
whitequark fe5fb34fae back.pysim: squash one level of hierarchy. 
There's really no point in the "top" node.
 2018-12-14 18:53:21 +00:00
whitequark 70ebc6f2c1 back.pysim: implement blocking assignment semantics correctly. 2018-12-14 18:47:12 +00:00
whitequark 120d817123 back.pysim: undriven sync signals should return to previous value. 2018-12-14 17:25:48 +00:00
whitequark 4f5b4a9bf4 back.pysim: in simulator sync processes, start by waiting for a tick. 
This matches Migen behavior and also makes more sense.
 2018-12-14 17:05:11 +00:00
whitequark e230383aac back.pysim: make initial phase configurable. 2018-12-14 16:46:16 +00:00
whitequark 0ef5ced492 compat.sim: match clock period. 2018-12-14 16:39:52 +00:00
whitequark 17d26c8329 compat: add run_simulation shim. 2018-12-14 16:22:18 +00:00
whitequark 88970ee29f pysim.back: fix add_sync_process wrapper to handle signals correctly. 2018-12-14 16:21:53 +00:00
whitequark 3bc3647380 compat.fhdl.module: fix specials. 2018-12-14 16:14:08 +00:00
whitequark 3b23645fb7 compat: add fhdl.specials.TSTriple shim. 2018-12-14 16:09:51 +00:00
whitequark 7200346249 genlib.io: import TSTriple from Migen. 2018-12-14 16:09:51 +00:00
whitequark 50ba443f92 fhdl.ast: fix Switch with constant test. 2018-12-14 16:09:51 +00:00
whitequark a0d555a9fc compat: add genlib.cdc.MultiReg shim. 2018-12-14 16:01:38 +00:00
whitequark baba47251c compat.fhdl.module: update deprecation messages. 2018-12-14 16:01:38 +00:00
whitequark 9307a31678 back.pysim: Simulator({gtkw_signals→traces}=). 2018-12-14 15:23:22 +00:00
whitequark e3f32a1faf back.pysim: better naming. NFC. 2018-12-14 15:21:13 +00:00
whitequark 474d46ced8 back.pysim: implement most operators and add tests. 2018-12-14 14:21:22 +00:00
whitequark d9aaf0114b back.pysim: close .vcd/.gtkw files on context manager exit. 2018-12-14 13:59:03 +00:00
whitequark 1655b59d1b back.pysim: show more legible names for processes in errors. 2018-12-14 13:50:19 +00:00
whitequark 625c55a3b8 back.pysim: throw exceptions back at processes. 2018-12-14 13:43:25 +00:00
whitequark 654722ce14 back.pysim: add gtkw traces even more robustly. 2018-12-14 13:43:08 +00:00
whitequark 7d3f7f277a back.pysim: accept (and evaluate) generator functions. 2018-12-14 13:32:30 +00:00
whitequark 7fc9f98b98 back.pysim: skip VCD signal population if VCD is not requested. 2018-12-14 13:32:30 +00:00
whitequark 3ad79ec690 back.pysim: allow processes to evaluate expressions. 2018-12-14 13:32:30 +00:00
whitequark 151d079f01 fhdl.ir: oops, we defined DomainError twice. 2018-12-14 12:59:54 +00:00
whitequark dd00b5e2d6 back.pysim: more general clean-up. 2018-12-14 12:46:04 +00:00
whitequark 1b7f8c7950 back.pysim: general clean-up. 2018-12-14 12:22:03 +00:00
whitequark 105113f1d8 back.pysim: accept any valid assignments from processes. 2018-12-14 12:18:41 +00:00
whitequark 240a40c2c2 back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw. 2018-12-14 10:57:13 +00:00
whitequark 7d91dd56c8 fhdl.xfrm: implement DomainLowerer. 2018-12-14 10:56:53 +00:00
whitequark b34c1a9ad0 back.pysim: undriven comb signals should return to reset value. 2018-12-14 09:12:38 +00:00
whitequark b58715c5dc ast, back.pysim: allow specifying user-defined decoders for signals. 2018-12-14 09:02:29 +00:00
whitequark bb843cb40c back.pysim: fix completely broken codegen for Switch. 2018-12-14 08:51:36 +00:00
whitequark 6aefd0c04c back.pysim: raise an exception if delta cycles blow a process deadline. 2018-12-14 08:10:21 +00:00
whitequark a10791e160 back.pysim: if requested, write a gtkw file with a useful preset. 2018-12-14 08:04:29 +00:00
whitequark cb998d891b back.pysim: explain how delta cycles work. 2018-12-14 07:26:26 +00:00
whitequark e4d08d2855 back.pysim: delay clock processes by one half period. 
Makes it easier to see initial delta cycles.
 2018-12-14 05:17:43 +00:00
whitequark 3bb7a87e0f back.pysim: implement "sync processes", like migen.sim generators. 2018-12-14 05:13:58 +00:00
whitequark d791b77cc8 back.pysim: allow suspending processes until a tick in a domain. 2018-12-14 04:33:06 +00:00
whitequark 3e59d857e1 back.pysim: use bare ints for signal values (-5% runtime). 2018-12-14 03:05:57 +00:00
whitequark b09f4b10ee back.pysim: collect handlers before running (-5% runtime). 2018-12-13 18:34:44 +00:00
whitequark a7ebc02bdd back.pysim: allow multiple registered handlers per signal. 2018-12-13 18:28:11 +00:00
whitequark 6a4004ef8d back.pysim: fix handling of process termination. 2018-12-13 18:17:58 +00:00
whitequark fb27c2520b back.pysim: new simulator backend (WIP). 2018-12-13 18:02:46 +00:00
whitequark 71f1f717c4 fhdl.cd: rename ClockDomain signals together with domain. 2018-12-13 15:24:55 +00:00
whitequark 07c818e077 fhdl.ir: move Fragment prepare logic from back.rtlil. 2018-12-13 14:34:07 +00:00
whitequark ac498414ab back.verilog: remove debug code. 2018-12-13 13:42:54 +00:00
whitequark 90f1503c91 fhdl.ir: record port direction explicitly. 
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
 2018-12-13 13:12:31 +00:00
whitequark 6251c95d4e compat.genlib.fsm: import/wrap Migen code. 2018-12-13 12:41:19 +00:00
whitequark 9661e897e6 fhdl.ir: a subfragment's input that we don't drive is also our input. 2018-12-13 11:50:56 +00:00
whitequark bb04c9e0da fhdl, back: trace and emit source locations of values. 2018-12-13 11:44:06 +00:00
whitequark 859c2dbcf0 back.rtlil: never give subfragment cells names starting with $. 2018-12-13 11:30:16 +00:00
whitequark b150f1915d fhdl.ir: don't crash propagataing ports in empty fragments. 2018-12-13 11:25:49 +00:00
whitequark 72257b6935 fhdl.ir: implement clock domain propagation. 2018-12-13 11:01:03 +00:00
whitequark fde2471963 fhdl.ir: remove iter_domains(). 2018-12-13 10:18:57 +00:00
whitequark f4340c19bb fhdl: cd_name→domain. 2018-12-13 10:15:01 +00:00
whitequark c5087edfa5 fhdl.cd: add tests. 2018-12-13 09:19:16 +00:00
whitequark 9bee90f1bd fhdl.xfrm: implement DomainRenamer. 2018-12-13 08:57:14 +00:00
whitequark 8963ab5d9f fhdl.xfrm: add test for ControlInserter with subfragments. 2018-12-13 08:45:10 +00:00
whitequark 19aa404628 fhdl.xfrm: add tests for ResetInserter, CEInserter. 2018-12-13 08:39:02 +00:00
whitequark b1a89ef5fd fhdl.ir: add tests for port propagation. 2018-12-13 08:09:39 +00:00
whitequark a797e27573 fhdl.dsl: add tests for lowering. 99% branch coverage. 2018-12-13 07:33:59 +00:00
whitequark d2e2d00e45 fhdl.cd: rename ClockDomain.{reset→rst}. 2018-12-13 07:27:27 +00:00
whitequark e0a81edf4d fhdl.dsl: add tests for submodules. 2018-12-13 07:24:28 +00:00
whitequark 932f1912a2 fhdl.dsl: use less error-prone Switch/Case two-level syntax. 2018-12-13 07:11:06 +00:00
whitequark f70ae3bac5 fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else. 2018-12-13 06:06:51 +00:00
whitequark 5b8708017e fhdl.ast: fix Switch._?hs_signals() for switch without statements. 2018-12-13 05:00:44 +00:00
whitequark 4e32f6b8de back.verilog: detect undriven public wires using Yosys. 
This should never happen, and is certainly a logic bug in nMigen.
 2018-12-13 04:59:48 +00:00
whitequark 27d3dfc453 back.rtlil: fix swapped operands in sync assign. 2018-12-13 04:34:22 +00:00
whitequark 6c7f98e964 back.rtlil: explain logic for CD reset insertion. 2018-12-13 03:51:00 +00:00
whitequark 2c67a620ee back.rtlil: explicitly set the top module. 2018-12-13 03:50:04 +00:00
whitequark 4df5c5de65 fhdl.ir: explain how port enumeration works. 2018-12-13 03:31:13 +00:00
whitequark f86ec1e7ef back.rtlil: explain how RTLIL conversion works. 2018-12-13 03:22:01 +00:00
whitequark bfd0011aee fhdl.ir: make sure clocks and resets of used CDs appear as inputs. 2018-12-13 02:43:22 +00:00
whitequark a17a9e355d back.rtlil: give clocks and resets nicer names. 2018-12-13 02:43:02 +00:00
whitequark 22c76e5f90 compat.fhdl.module: implement finalization. 2018-12-13 02:36:15 +00:00
whitequark b42620e490 back.rtlil: match shape of $mux ports A/B/Y. 2018-12-13 02:35:46 +00:00
whitequark 17767642be tracer: add support for Python 3.7. 2018-12-13 02:20:00 +00:00
whitequark f0f4c0ce61 fhdl.ast: bits_sign→shape. 2018-12-13 02:06:58 +00:00
whitequark dc486ad8b9 fhdl.ast: add tests for most logic. 2018-12-13 02:06:55 +00:00
whitequark b4dab74b2e compat.fhdl.{module,structure}: import/wrap Migen code (WIP). 2018-12-12 15:47:34 +00:00
whitequark 356852a570 compat.fhdl.bitcontainer: import/wrap Migen code. 2018-12-12 15:22:34 +00:00
whitequark 1d4d00aac6 fhdl.ast.Signal: implement .like(). 2018-12-12 14:43:19 +00:00
whitequark ad9b45adcd fhdl.ir: fix port threading code. 2018-12-12 13:00:50 +00:00